IDT72T54262L6-7BB IDT, Integrated Device Technology Inc, IDT72T54262L6-7BB Datasheet - Page 47

• Manufacturer Part Number: IDT72T54262L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54262L6-7BB

• Function: Asynchronous
• Memory Size: 5.2K (262 x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54262L6-7BB

WCLK0
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. t
3. First data word latency = t
4. OE0 = LOW.
5. RCLK0 must be free running for EF0 to update.
6.
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
RCLK0
WEN0
REN0
RCS0
Q[9:0]
D[9:0]
the rising edge of WCLK0 and the rising edge of RCLK0 is less than t
SKEW1
EF0
MD
1
is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that EF0 will go HIGH (after one RCLK0 cycle plus t
t
t
ENS
ENS
D/C
t
RCSLZ
IW
OW
D/C
t
ENH
SKEW1
Figure 24. Read Cycle and Read Chip Select (Quad mode, IDT Standard mode, SDR to SDR)
t
A
+ 1*T
WDDR
0
RCLK
LAST DATA-1
RDDR
+ t
0
REF.
FWFT/SI
t
CLKH
0
t
RCSHZ
t
CLK
t
t
ENS
CLKL
SKEW1
t
RCSLZ
, then EF0 deassertion may be delayed one extra RCLK0 cycle.
™
t
47
REF
DDR/SDR FIFO
t
A
t
ENH
t
ENS
t
DS
D
x
LAST DATA
t
SKEW1
t
t
DH
ENH
(2)
1
t
RCSHZ
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
2
t
REF
FEBRUARY 11, 2009
REF
). If the time between
6158 drw29