MT29F1G08ABBHC-ET Micron, MT29F1G08ABBHC-ET Datasheet - Page 22

• Manufacturer Part Number: MT29F1G08ABBHC-ET
• Description: NAND Flash Memory; Density: 1Gb; Organization: 128Mbx8; Bits/Cell: SLC; I/O: Common; Supply Voltage: 1.8V; Operating Temperature Range: -40° to +85°C; Package: 63-VFBGA
• Manufacturer: Micron

RANDOM READ 05h-E0h
Figure 13:
PAGE READ CACHE MODE START 31h; PAGE READ CACHE MODE START LAST 3Fh
PDF: 09005aef81dc05df / Source: 09005aef821d5f08
1gb_nand_m48a__2.fm - Rev. E 1/08 EN
R/B#
I/Ox
RE#
00h
RANDOM DATA READ Operation
(4 cycles)
Address
30h
The RANDOM READ command enables the user to specify a new column address so
data at single or multiple addresses can be read. The random read mode is enabled after
a normal PAGE READ (00h-30h sequence).
Random data can be output after the initial PAGE READ by writing an 05h-E0h com-
mand sequence along with the new column address (2 cycles).
The RANDOM READ command can be issued without limit within the page.
Only data on the current page can be read. Pulsing RE# outputs data in the same manner
as a serial PAGE READ (see Figure 13).
Micron NAND Flash devices have a cache register that can be used to increase READ
operation speed when accessing sequential pages in a block.
A normal PAGE READ (00h-30h) command sequence is issued (see Figure 14 on page 23
for details). The R/B# signal goes LOW for
page of data from the memory to the data register. After R/B# returns to HIGH, the PAGE
READ CACHE MODE START (31h) command is latched into the command register. R/B#
goes LOW for
cache register. When the data register contents are transferred to the cache register,
another PAGE READ is automatically started as part of the 31h command. Data is trans-
ferred from the memory array to the data register at the same time data is being output
(pulsing of RE#) from the cache register. If the total time to output data exceeds
the PAGE READ is hidden.
The second and subsequent pages of data are transferred to the cache register by issuing
additional 31h commands. R/B# will stay LOW up to
depending on whether the previous memory-to-data-register transfer was completed
before issuing the next 31h command. If the data transfer from memory to the data reg-
ister is not completed before the 31h command is issued, R/B# stays LOW until the
transfer is complete.
It is not necessary to output a whole page of data before issuing another 31h command.
R/B# will stay LOW until the previous PAGE READ is complete and the data has been
transferred to the cache register.
To read out the last page of data, the PAGE READ CACHE MODE START LAST (3Fh) com-
mand is issued. This command transfers data from the data register to the cache register
without another PAGE READ (see Figure 14 on page 23 for details).
t R
t
DCBSYR1 while data is being transferred from the data register to the
Data output
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
05h
t
R during the time it takes to transfer the first
1Gb: x8, x16 NAND Flash Memory
(2 cycles)
Address
t
DCBSYR2. This time can vary,
E0h
Command Definitions
©2006 Micron Technology, Inc. All rights reserved.
Data output
t
R, then