MT29F1G08ABBHC-ET Micron, MT29F1G08ABBHC-ET Datasheet - Page 10

• Manufacturer Part Number: MT29F1G08ABBHC-ET
• Description: NAND Flash Memory; Density: 1Gb; Organization: 128Mbx8; Bits/Cell: SLC; I/O: Common; Supply Voltage: 1.8V; Operating Temperature Range: -40° to +85°C; Package: 63-VFBGA
• Manufacturer: Micron

Table 1:
PDF: 09005aef81dc05df / Source: 09005aef821d5f08
1gb_nand_m48a__2.fm - Rev. E 1/08 EN
I/O[15:0]
Symbol
I/O[7:0]
LOCK
(x16)
WE#
WP#
R/B#
ALE
CE#
RE#
(x8)
CLE
V
V
NC
CC
SS
Ball Descriptions
Output
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Type
I/O
–
Ball Function
Address latch enable: During the time ALE is HIGH, address information is
transferred from I/O[7:0] into the on-chip address register. Upon a LOW to HIGH
transition on WE#—when address information is not being loaded—the ALE signals
should be driven LOW.
Chip enable: Gates transfers between the host system and the NAND Flash device.
After the device becomes busy or starts a PROGRAM or ERASE operation, CE# can be
de-asserted. See “Bus Operation” on page 16 for additional operational details.
Command latch enable: When CLE is HIGH, information is transferred from
I/O [7:0] to the on-chip command register on the rising edge of WE#. When
command information is not being loaded, the CLE signals should be driven LOW.
When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled.
To disable BLOCK LOCK, connect LOCK to V
unconnected (internal pull-down).
Read enable: Gates transfers from the NAND Flash device to the host system.
Write enable: Gates transfers from the host system to the NAND Flash device.
Write protect: Protects against inadvertent PROGRAM and ERASE operations. All
PROGRAM and ERASE operations are disabled when WP# is LOW.
Data inputs/outputs: Bidirectional I/O signals transfer address, data and instruction
information. Data is output only during READ operations; at other times the I/O
signals are inputs.
Ready/busy: The ready/busy signal is an open-drain, active-LOW output, that uses an
external pull-up resistor. The signal is used to indicate when the chip is processing a
PROGRAM or ERASE operation. The signal is also used during READ operations to
indicate when data is being transferred from the array into the serial data register.
When these operations have completed, the ready/busy signal returns to the high-
impedance state.
V
V
No connect: NC balls are not internally connected. These balls can be driven or left
unconnected.
CC
SS
: The V
: The V
SS
CC
ball is the ground connection.
ball is the power supply.
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x8, x16 NAND Flash Memory
SS
during power-up, or leave it
General Description
©2006 Micron Technology, Inc. All rights reserved.