AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 51

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

SPORTx IOP Register Clear Init Routine
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/* ADSP-21161 system Register bit definitions */
#include
.GLOBAL
.section /pm
Clear_All_SPT_Regs:
ROUTINE TO CLEAR AND RESET ALL SPORT1 REGISTERS
This routine simply clears all SPORT0/1 ctrl and DMA registers back to their
default states so that we can reconfigure it for our AD1836 application.
John Tomarakos
ADI DSP Applications
Rev 1.0
4/30/99
IRPTL = 0x00000000;
bit clr imask SP0I|SP1I|SP2I|SP3I;
R0 = 0x00000000;
dm(SPCTL0) = R0;
dm(SPCTL1) = R0;
dm(SPCTL2) = R0;
dm(SPCTL3) = R0;
dm(DIV0) = R0;
dm(DIV1) = R0;
dm(DIV2) = R0;
dm(DIV3) = R0;
/* SPORT 0 & 2 Miscellaneous Control Bits Registers */
R0 = 0x00000000;
dm(SP02MCTL) = R0;
dm(SP13MCTL) = R0;
/* sport0 receive multichannel word enable registers */
R0 = 0x00000000;
dm(MR0CS0) = R0;
dm(MR0CS1) = R0;
dm(MR0CS2) = R0;
dm(MR0CS3) = R0;
/* sport1 receive multichannel word enable registers */
R0 = 0x00000000;
dm(MR1CS0) = R0;
dm(MR1CS1) = R0;
dm(MR1CS2) = R0;
dm(MR1CS3) = R0;
/* sport2 transmit multichannel word enable registers */
R0 = 0x00000000;
dm(MT2CS0) = R0;
dm(MT2CS1) = R0;
dm(MT2CS2) = R0;
dm(MT2CS3) = R0;
/* sport3 transmit multichannel word enable registers */
R0 = 0x00000000;
dm(MT3CS0) = R0;
dm(MT3CS1) = R0;
dm(MT3CS2) = R0;
dm(MT3CS3) = R0;
/* sport0 receive multichannel companding enable registers */
R0 = 0x00000000;
dm(MR0CCS0) = R0;
dm(MR0CCS1) = R0;
"def21161.h"
Clear_All_SPT_Regs;
pm_code;
/* clear pending interrupts */
/* sport0 control register */
/* sport1 control register */
/* sport3 control register */
/* sport4 control register */
/* sport0 frame sync divide register */
/* sport1 frame sync divide register */
/* sport2 frame sync divide register */
/* sport3 frame sync divide register */
/* Enable SPORT loopback bit 12 */
/* multichannel mode disabled */
/* multichannel mode disabled */
/* multichannel mode disabled */
/* multichannel mode disabled */
/* no companding */
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