AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 49

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

SPORT_DMA_setup:
//
//
SPORT channel's transmit data buffer
words for transmission
//
8:4
2:1
bit clr IMASK SP1I | SP3I;
r0=0x00000000;
dm(SPCTL1)=r0;
dm(SPCTL3)=r0;
ustat1=dm(SPCTL3);
ustat2=dm(SPCTL1);
ustat3=dm(SP13MCTL);
r0=tx_buf3a;
r0=1;
r0=@tx_buf3a;
r0=rx_buf1a;
r0=1;
r0=@rx_buf1a;
/* clear multichannel/miscellaneous control register for SPORT1 & SPORT3 */
R0 = 0x0;
/*internally generating FS3 and *HARDWARE* loop it back to FS1 for SPORT1/3 SPI control*/
/*
R0 = 0x00270004;
R0 = 0x000F003B;
R0 = 0x0011002B;
R0 = 0;
/* SPCTL3 SPORT CONTROL REGISTER BITs
31:26
25
24
23
22
21:20
19
18
17
16
15
14
13
12
11
10
R0 = 0x020374F1;
bit set ustat1 DDIR | SDEN_A | LAFS | LFS |
dm(SPCTL3) = ustat1;
/* SRCTL0 SPORT CONTROL REGISTER BITs
31:26
25
24
23
22
21:20
19
18
17
16
15
Maximum SPI serial bit clock rate is 8MHz...
according to 9-42 of user's manual, xCLKDIV = ((2 x fCLKIN)/(serial clock frequency)) - 1
Thus, xCLKDIV = ((2 x 30 MHz)/(1 MHz)) - 1 = 59 = 0011 1011 (binary) = 0x003B
Now, since we want 16 bit clocks per frame, set FSDIV to 16-1 = 15 = 0x000F */
9
3
0
-- DMA chaining and DMA enables for Channel B: 0:0 Disabled
-- DMA chaining and DMA enables for Channel B: 0:0 Disabled
-- Read-only status bits
-- Read-only status bits
dm(II3A)=r0;
dm(IM3A)=r0;
dm(C3A)=r0;
dm(II1A)=r0;
dm(IM1A)=r0;
dm(C1A)=r0;
-- DDIR Bit = 1, Transmitter
-- SPORT Enable B: 0 Disabled
-- reserved
-- Word Select: 0 issue if data in either Tx
-- SPORT xmit DMA chaining enable A:
-- SPORT xmit DMA enable A:
-- Late FS:
-- Active Low FS:
-- TFS data dependency: 0 TFS signal generated only when new data is in
-- IFS Source: 1 internal
-- FSR Requirement:
-- Active Clock Edge:
-- Operation mode:
-- Xmit Clk source:
-- 16/32-bit pack:
-- Serial Word Length minus 1:
-- Endian word format:
-- Data Type:
-- SPORT Enable A:
-- DDIR Bit = 0, Receiver
-- SPORT Enable B: 0 Disabled
-- MCE - SPORT Mode:
-- SPORT Loopback:
-- SPORT Rcv DMA chaining enable A:
-- SPORT Rcv DMA enable A:
-- Late RFS:
-- Active Low RFS:
-- reserved
dm(SP13MCTL) = R0;
dm(DIV3) = R0;
dm(DIV3) = R0;
dm(DIV3) = R0;
dm(DIV1) = R0;
1 Late (see p.7 of 1836 data sheet)
1 Late (see p.7 of 1836 data sheet)
/* Internal DMA6 memory address
/* Internal DMA6 memory access modifier
/* Contains number of DMA6 transfers to be done */
/* Internal DMA2 memory address
/* Internal DMA2 memory access modifier
/* Contains number of DMA2 transfers to be done */
0:0 r-justify; fill MSBs w/0s
1 Active Low
0 non-I2S mode
0 no unpacking of 32-bit words into separate 16-bit
1 enable A
0 disable
1 Active Low (again, see p.7 of...)
1 FS required
1 internal
0 DSP SPORT Mode
1 rising edge
0 MSB first
// initially clear SPORT control register
IFS | FSR | CKRE | ICLK | SLEN16 | SPEN_A;
select 1 MHz to allow safety factor of 8
01111
*/
0 disable
0 disable
0 disabled
0 disabled
*/
*/
*/
*/