AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 25

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

Note that the count and modified values can be initialized in the buffer declaration so that they are resident after a DSP reset
and boot. However, at runtime, further modification of the buffer is required to initiate the DMA autobuffer process.
To setup and initiate a chain of SPORT DMA operations at runtime, the ADSP-21161 program should follow this sequence:
1.
2.
3.
The DMA interrupt request occurs whenever the Count Register decrements to zero.
SPORT DMA chaining occurs independently for the transmit and receive channels of the serial port. After the SPORT1
receive buffer (rx_buf0a) is filled with new data, a SPORT1 receive interrupt is generated, and the data placed in the receive
buffer is available for processing. The DMA controller will autoinitialize itself with the parameters set in the TCB buffer and
begin to refill the receive DMA buffer with new data in the next audio frame. The processed data is then placed in the SPORT
transmit buffer, where it will then be DMA’ed out from memory to the SPORT DT1A pin. After the entire buffer is
transmitted, the DMA controller will autoinitialize itself with the stored TCB parameters to perform another DMA transfer of
new data that will be placed in the same transmit buffer (tx_bu2a).
Below are the assembly instructions used in the EZ-KIT assembly codec driver (listed in shown in appendix A) to set up the
receive transmit DMA buffers and Transfer Control Blocks for SPORT0 and SPORT2 Channel A. These values are reloaded
from internal memory to the DMA controller after the entire SPORT DMA buffer has been received or transmitted. SPORT0
is assumed to be configured as a receive DMA channel, while SPORT2 is configured as a transmit DMA channel.
.segment
/* define DMA buffer sizes to match number of active TDM channels */
.var
.var
/* DMA Chaining Transfer Control Block (TCB) */
/* TCB format: Ecx (length of destination buffer),
Set up SPORT transmit and Receive TCBs (transfer control blocks). The TCBs are defined in the data variable declaration
section of your code. Before setting up the values in the TCB and kicking off the DMA process, make sure the SPORT
registers are programmed along with the appropriate chaining bits required in step 2.
Write to the SPORT0/2 control registers (SPCTL0 and SPCTL2), setting the SDEN_A and/or SDEN_B enable bit to 1 and
the SCHEN_A and/or SCHEN_B chaining enable bit to a 1.
Write the address of the Iixxx register of the first TCB to the CPxxx register to start the chain. The order should be as
follows:
rx0a_buf[8];
tx2a_buf[8] =
a) write the starting address of the SPORT DMA buffer to the TCBs internal index register Iixxx location (TCB
b) write the DMA modify register value Imxxx to the TCB (TCB buffer base address + 6). Note that this step may
c) write the DMA count register Cxxx value to the TCB (TCB buffer base address + 5). Also note that this step may
d) get the Iixxx value of the TCB buffer that was previously stored in step (a), set the PCI bit with a that internal
e) write the same ‘PCI-bit-set’ internal address value from step (d) manually into that DMA channels chain pointer
/dm
buffer base address + 7). You need to get the starting address of the defined DMA buffer at runtime and copy it
into this location in the TCB.
be skipped if it the location in the buffer was initialized in the variable declaration section of your code.
be skipped if it the location in the buffer was initialized in the variable declaration section of your code.
address value, and write the modified value to the chain pointer location in the TCB (TCB buffer base offset + 4).
register (CPxxx). At this moment the DMA chaining begins.
dm_codec;
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000;
/* receive buffer (DMA)*/
/* transmit buffer (DMA)*/