AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 32

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

4.1 Configuring The AD1836 Serial Link To TDM Mode For ADI SPORT Compatibility
The Extended TDM Mode allows an efficient communication interface between DSP and the AD1836. This mode of operation
works efficiently with the use of serial port "autobuffering" or "DMA chaining." With this mode all 8 slots are 32-bits,
allowing a simple interface to 32-bit DSPs like the ADSP-21161 with it's 32-bit serial shift registers. The DSP will generate a
frame sync every 256 serial clock cycles.
The DSP will generate a frame sync every 256 serial clock cycles. With an SCLK running at 12.288 MHz, the DSP will then
produce the 48KHz frame sync. Please note that in Extended TDM mode, 96 kHz sampling rates are not supported. To take
advantage of this feature, you must use I
By default, the AD1836 is in I
initially program the AD1836 for TDM mode as soon as the codec is operational (after a powerup reset or powerdown).
#define
#define
.var tx_buf[9] = ENABLE_Vfbit_SLOT1_SLOT2,
4.2
The ADSP-21161 EZ-KIT lite allows the programming of the AD1836 registers via SPORT1 and SPORT3. This SPI
emulation works well for the AD1836 extra clock requirement to latch data, because the SPORTs generate a continuous clock.
The AD1836 does not care about a continous clock since the data is latched 1 cycle after the DSP's inverted frame sync goes
high. To program the AD1836 registers, the SPORTs are programmed as follows:
SPORT3 Control Register (Configured as a transmitter)
SPORT1 Control Register (Configured as a receiver)
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8 x 32-bit timeslots = 256 bit clock cycles
Programming the ADSP-21161 SPORT1/SPORT3 for "SPI Emulation" to
Communicate with the AD1836 SPI-Compatible Port
Late Frame Sync (Late FS3 and Active Low FS3 emulates the CLATCH operation)
Data Dependent Frame Sync
Internal Frame Sync
Internal SCLK3
16-bit words
Late Frame Sync
Active Low Frame Sync
External Frame Sync
External SCLK1 (tied together with SCLK3)
External FS1 (tied together with FS3)
16-bit words
SERIAL_CONFIGURATION
ENABLE_Vfbit_SLOT1_SLOT2
SERIAL_CONFIGURATION,
0xFF80,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000;
2
S mode. To initially configure the AD1836 to conform to DSP TDM schemes, the DSP should
2
S mode using up to 3 ADSP-21161 SPORTs (depending on the # of outputs required).
/* initially set to SLOT-16 mode for ADI SPORT compatibility*/
0x7400
0xE000
/* set valid bits for slot 0, 1, and 2 */
/* serial configuration register address 0x74 */
/* stuff other slots with zeros for now */