AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 35

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

5.1 Programming AD1836 Registers Using A Zero Overhead Loop Construct
The following assembly language hardware DO LOOP shows how the values in the Init_Codec_Registers[ ] buffer are sent to
the appropriate slots on the Serial Port TDM bus:
/* Buffer holds SPI codes to write to each of 15 internal registers on 1836 */
.VAR
_______________________________________________
// Example Core-based loop via SPORT3
Program_AD1836_Registers:
Set_1836_Regs: nop;
_______________________________________________
// Example Core-based loop via SPI
Program_AD1836_Registers:
Set_1836_Regs: nop;
Explanation Of The AD1836 Codec Initialization Loop :
•
•
•
The buffer pointer is first set to point to the top of the codec register buffer.
The Loop Counter Register LCNTR is set to the number of registers to be programmed. In this case 11 registers are
programmed.
Memory writes to DM(TX3A) or DM(SPITX) will program the codec register address
Init_Codec_Registers[15] =
DAC_CONTROL1 | WRITE_REG | 0x000,
DAC_CONTROL1 | WRITE_REG | 0x000,
DAC_CONTROL2 | WRITE_REG | 0x000,
DAC_VOLUME0
DAC_VOLUME1
DAC_VOLUME2
DAC_VOLUME3
DAC_VOLUME4
DAC_VOLUME5
ADC_CONTROL1 | WRITE_REG | 0x000,
ADC_CONTROL1 | WRITE_REG | 0x000,
ADC_CONTROL3 | WRITE_REG | 0x040,
ADC_CONTROL2 | WRITE_REG | 0x380,
ADC_CONTROL2 | WRITE_REG | 0x380;
M7 = 1;
I7 = Init_Codec_Registers;
L7 = 0;
lcntr = 15, DO Set_1836_Regs until LCE;
M7 = 1;
I7 = Init_Codec_Registers;
L7 = 0;
lcntr = 15, DO Set_1836_Regs until LCE;
ADC2_PEAK_LEVEL | READ_REG | 0x000,
ADC3_PEAK_LEVEL | READ_REG | 0x000,
ADC_CONTROL1
ADC_CONTROL2
ADC_CONTROL3
r13 = dm(I7,M7);
DM(TX3A) = r13;
idle;
r13 = dm(I7,M7);
DM(SPITX) = r13;
idle;
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| WRITE_REG | 0x3FF,
| READ_REG | 0x000,
| READ_REG | 0x000,
| READ_REG | 0x000;
// we "OR" in address, rd/wr, and register data
// for ease in reading register values
// write DAC_CTL1 twice to workaround pwdwn SPI anomaly
// write ADC_CTL1 twice to workaround pwdwn SPI anomaly
// 512*Fs Clock Mode !!!, differential PGA mode
// SOUT MODE = 110 --> TDM Mode, Master device