AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 34

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

5.
Addr.
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
** Registers highlighted in bold have been altered from their default states by the 21161 for the talkthru example. Other registers set by the DSP that are
not highlighted but marked with a Y are set to their default reset state and are user configurable. All other registers marked with a N are not set by the
DSP.
All addressable codec control registers that are used are initially set by the ADSP-21161 using a DSP memory buffer, where all
register addresses stored on even number memory buffer locations, and their corresponding register data stored at adjacent odd
numbered memory locations in the buffer. In the 21161 example, 11 registers are programmed during codec initialization.
In the ADI supplied drivers, many AD1836 registers are not modified from their default power-up initialization values. The
ADC Control 2 register is programmed to a value of 0x380, which alters the AD1836 serial protocol from I
Extended TDM mode of operation. Notice that ADC Control register 3 is programmed to ensure the clock mode is 256 x f2
with a 12.288 MHz crystal, which is the value used on the revision 1.1 21161 EZ-KIT Lite boards. This value would change
depending on if the user wishes to use a 24.576 MHz crystal. Also, the DAC Control 2 and the ADC Control 1 registers should
be written to twice after a AD1836 power-down sequence to properly initialize the register (refer to the AD1836 anomaly list
for more information).
The assembly language buffer initialization is shown below:
.var tx_buf3a[21] = //program register commands
DSP Programming Of The AD1836 Control/Status Registers
Codec Register Name
DAC Control 1
DAC Control 2
DAC Volume 0
DAC Volume 1
DAC Volume 2
DAC Volume 3
DAC Volume 4
DAC Volume 5
ADC 0 - Peak Level (Read Only)
ADC 1 - Peak Level (Read Only)
ADC 2 - Peak Level (Read Only)
ADC 3 - Peak Level (Read Only)
ADC Control 1
ADC Control 2
ADC Control 3
Reserved
DAC_CONTROL1 | WRITE_REG | 0x000, // we "OR" in address, rd/wr, and register data
DAC_CONTROL1 | WRITE_REG | 0x000, // for ease in reading register values
DAC_CONTROL2 | WRITE_REG | 0x000, // write DAC_CTL1 twice to workaround pwdwn SPI anomaly
DAC_VOLUME0 | WRITE_REG | 0x3FF,
DAC_VOLUME1 | WRITE_REG | 0x3FF,
DAC_VOLUME2 | WRITE_REG | 0x3FF,
DAC_VOLUME3 | WRITE_REG | 0x3FF,
DAC_VOLUME4 | WRITE_REG | 0x3FF,
DAC_VOLUME5 | WRITE_REG | 0x3FF,
ADC_CONTROL1 | WRITE_REG | 0x000, // write ADC_CTL1 twice to workaround pwdwn SPI anomaly
ADC_CONTROL1 | WRITE_REG | 0x000,
ADC_CONTROL3 | WRITE_REG | 0x000, // 256*Fs Clock Mode !!!, differential PGA mode
ADC_CONTROL2 | WRITE_REG | 0x380, // SOUT MODE = 110 --> TDM Mode, Master device
ADC_CONTROL2 | WRITE_REG | 0x380,
// read register commands
ADC0_PEAK_LEVEL | READ_REG | 0x000, // status will be in rx_buf1a[13-19] memory locations
ADC1_PEAK_LEVEL | READ_REG | 0x000,
TABLE 10. AD1836 Driver Register States
#define label in 21161 program
DAC_CONTROL1
DAC_CONTROL2
DAC_VOLUME0
DAC_VOLUME1
DAC_VOLUME2
DAC_VOLUME3
DAC_VOLUME4
DAC_VOLUME5
ADC0_PEAK_LEVEL
ADC1_PEAK_LEVEL
ADC3_PEAK_LEVEL
ADC_CONTROL1
ADC_CONTROL2
ADC_CONTROL3
RESERVED_REG
ADC2_PEAK_LEVEL
data bits D9:D0
0x000
0x000
0x3FF
0x3FF
0x3FF
0x3FF
0x3FF
0x3FF
0x000
0x000
0x000
0x000
0x000
0x380
0x000
0x000
modified by DSP?
2
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N
S mode into