AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 43

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

6.3 Processing 24-bit Data In 1.31 Fractional Format Or IEEE 32-bit Floating Point Format
Data that is received or transmitted in the SPORT1 ISR is in a binary, 2's complement format. The DSP interprets the data in
fractional format, where all #s are between -1 and 0.9999999. Initially, the serial port places the data into internal memory in
data bits D0 to D15. In order to process the fractional data in 1.31 format, the AD1836 left justifies the 24-bit data to the upper
32-bits of the timeslot data-word. This makes it simple to take advantage of the fixed-point multiply/accumulator's fractional
1.31 mode, as well as offer an easy reference for converting from 1.31 fractional to floating point formats. This also guarantees
that any quantization errors resulting from the computations will remain well below the 24-bit result and thus below the
AD1836 DACs' 105 dB Noise Floor. After processing the data, the 1.31 fractional result is then sent to the AD1836, where the
AD1836 will truncate the 32-bit dataword to 24-bits before DAC conversion. Below are example instructions to demonstrate
shifting of data before and after the processing of data on the Master AD1836 left channel:
32-bit Fixed Point Processing
r1 = dm(rx_buf0a + Internal_ADC_L0);
dm(Left_Channel_In0)=r1;
/*
[Call Fixed_Point_Algorithm]
r15 = dm(Left_Channel_Out0);
dm(tx_buf2a + Internal_DAC_L0) = r15;
32-bit Floating Point Processing
To convert between our assumed 1.31 fractional number and IEEE floating point math, here are some example
assembly instructions.
format, as shown above:
r1 = -31;
r0 = DM(Left_Channel_In0);
f0 = float r0 by r1;
[Call Floating_Point_Algorithm]
r1 = 31;
r8 = fix f8 by r1;
DM(Left_Channel_Out0) = r8;
REFERENCES
The following sources contributed information to this applications note:
[1] L. D. Fielder, "Human Auditory Capabilities and Their Consequences in Digital-Audio Converter Design", Audio in Digital Times, Proc. Audio
En g. Soc. 7
[2] Analog Devices Whitepaper, ADSP-21065L: Low-Cost 32-bit Processing for High Fidelity Digital Audio, Analog Devices, 3 Technology Way,
Norwood, MA, November 1997
[3] R. Wilson, “Filter Topologies”, J. Audio Engineering Society, Vol 41, No. 9, September 1993
[4] J. Dattorro, “The Implementation of Digital Filters for High Fidelity Audio”, Audio in Digital Times, Proc. Audio En g. Soc. 7
Toronto, Ont., Canada, May 14
[5] Udo Zolzer, “Roundoff Error Analysis of Digital Filters”, J. Audio Engineering Society, Vol42, No. 4, April 1994
[6] K. L. Kloker, B. L. Lindsley, C.D. Thompson, “VLSI Architectures for Digital Audio Signal Processing,” Audio in Digital Times, Proc. Audio En
g. Soc. 7
[7] Chen, C, “Performance of Cascade and Parallel IIR Filters,” Jour Audio Eng Soc, March 1996, Vol 44, No 3.
[11] Gary Davis & Ralph Jones, Sound Reinforcement Handbook, 2nd Edition”, Ch. 14, pp. 259-278, Yamaha Corporation of America, (1989,
1990)
8] ADSP-21161 SHARC DSP Hardware Reference Manual, Second Edition, June 2001, Analog Devices, Inc., (82-001944-02)
[9] AD1836 Data Sheet, Analog Devices, Inc,.
Process data here, data is processed in 1.31 format */
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Inter. Conf., Toronto, Ont., Canada, May 14
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Inter. Conf., Toronto, Ont., Canada, May 14
<-- scale the sample to the range of +/-1.0
<-- scale the result back up to MSBs
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This assumes that our AD1836 data has already been converted to floating point
-17
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1989, pp. 165-180.
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-17
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-17
/* get AD1836 left channel ADC0 input sample */
/* save to data holder for processing */
/* get channel 1 output result */
/* output left result to AD1836 left channel DAC0 */
1989, pp. 313-325
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1989, pp. 45-62.
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Inter. Conf.,