AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 24

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

3.6 Setting Up The ADSP-21161 DMA Controller For Chained SPORT DMA Transfers
To efficiently transmit and receive digital audio data to/from the AD1836, the recommended method is to use "Serial Port
DMA Chaining" to transfer data between the serial bus and the DSP core. There are obvious benefits for doing this. First of
all, DMA transfers allow efficient transfer of data between the serial port circuitry and DSP internal memory with zero-
overhead, i.e. there is no processor intervention of the SHARC core to manually transfer the data. Secondly, there is a one-to-
one correspondence of the location of the word in the transmit and receive SPORT DMA buffers with the actual TDM
audio frame timeslot on the serial bus. Thirdly, an entire block of data can be transmitted or received before generating a
single interrupt. The 'chained-DMA' method of serial port processing is more efficient for the SHARC to process data, versus
interrupt driven transfers, which occur more frequently and thus take up more overhead in servicing the audio data. Using
chained DMA transfers allows the ADSP-21161 DMA controller to autoinitialize itself between multiple DMA transfers.
When the entire contents of the current SPORT buffers rx_buf0a and tx_buf2a have been received or transmitted, the ADSP-
21161's I/O processor will automatically set up another serial port DMA transfer that is continuously repeated for every DMA
interrupt. For further information on DMA chaining, the reader can refer to "Chaining DMA Processes" section (pages 6-25 to
6-29 I/O Processor Chapter 6) in the ADSP-21161 Hardware Reference.
The chain pointer register (CPxxx) is used to point to the next set of TX and RX buffer parameters stored in memory. SPORT
DMA transfers for the AD1836 are initiated by writing the DMA buffer's memory address to the CP0A register for SPORT0
receive and CP2A register for SPORT2 transmit. The SCHEN_A and SCHEN_B bits in the SPORTx Control registers enable
DMA chaining.
To auto-initialize repetitive DMA-chained transfers, the programmer needs to set up a buffer in memory called a transfer
control block (TCB) that will be used to initialize and further continue the chained DMA process. Transfer Control Blocks are
locations in Internal Memory that store DMA register information in a specified order. For example, Figure 20 below
demonstrates defined TCBs in internal memory for SPORT1 Channel A. The Chain Pointer Register (CP0AA and CP2A)
stores the location of the next set of TCB parameters to be automatically be downloaded by the DMA controller at the
completion of the DMA transfer, which in this case it points back to itself.
These TCBs for both the transmit and receive buffers are can be defined in the variable declaration section of your code. In the
I2S example code shown in appendix A, the TCBs for SPORT1 channel A are defined as follows:
.var
.var
rcv1a_tcb[8]
xmit1a_tcb[8] = 0, 0, 0, 0, 0, 8, 1, tx_buf2a;
DM(rcv0a_tcb + 0)
DM(rcv0a_tcb + 1)
DM(rcv0a_tcb + 2)
DM(rcv0a_tcb + 3)
DM(rcv0a_tcb + 4)
DM(rcv0a_tcb + 5)
DM(rcv0a_tcb + 6)
DM(rcv0a_tcb + 7)
Figure 20. TCBs for Chained DMA Transfers
of SPORT1 Channel A Receive and Transmit
= 0, 0, 0, 0, 0, 8, 1, rx_buf0a;
rcv0a_tcb[8]
ECEPx (not used
with SPORTs)
EMEPx (not used
with SPORTs)
EIEPx (not used
with SPORTs)
GPR1A
CPR1A
CR1A
IMR1A
IIR1A
DM(xmit2a_tcb + 0)
DM(xmit2a_tcb + 0)
DM(xmit2a_tcb + 0)
DM(xmit2a_tcb + 0)
DM(xmit2a_tcb + 0)
DM(xmit2a_tcb + 0)
DM(xmit2a_tcb + 0)
DM(xmit2a_tcb + 0)
/* SPT0 receive tcb */
/* SPT2 transmit tcb */
xmit2a_tcb[8]
GPT1A
CPT1A
CT1A
IMT1A
IIT1A