AN1836-AN21161 Analog Devices, AN1836-AN21161 Datasheet - Page 30

• Manufacturer Part Number: AN1836-AN21161
• Description: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec
• Manufacturer: Analog Devices

Due to the current AD1836 SPI anomaly, the 21161 EZ-KIT Lite reference source codes uses the second method shown above
for interfacing the the AD1836's SPI slave port. Using SPORT1 and SPORT 3 to communicate allows us to "trick" the
AD1836 to emulate an SPI master protocol with a continuous clock. Thus the serial port interface will guarantee that an extra
serial clock is present after the inverted frame sync on the SPORT goes high. The clock cycle after the frame sync going high
will properly latch AD1836 register data.
Figure X below shows the timing for the AD1836 slave port. The AD1836's SPI interface consists of CLATCH (SPI device
select), CCLK (SPI serial clock), CDATA (SPI slave in data), and COUT (SPI slave out data). The Serial SPI word format
consists of 16 bit words, starting with MSB first. For codec register writes, the data written is 16-bits. For codec register reads,
the AD1836 will respond to a read command by driving a 10-bit word. Notice that the current revision AD1836 silicon
requires the extra CCLK after CLATCH high. The next revision of AD1836 will address this issue so that the extra clock is not
required, and data will be latched in the CCLK cycle in which the D0 bit is transmitted.
Figure 24. SPI Slave Interface Timing Diagram
Figure X below shows the Serial SPI word format for codec register commands.
There are 16 internal registers on the
AD1836. The register addresses are located in bits D12 to D15 in the SPI serial word. To initiate read or write commands, bit
D11 is either set (for reads) or cleared (for writes). Bit 10 is reserved and should always be set to 0 by the master SPI device.
Codec register addressed data is 10 bits in length and are accessed in data bits D9 to D0.
Figure 25. AD1836 Slave SPI Word Format