LM3S2110-IQN20-A0 Luminary Micro, Inc., LM3S2110-IQN20-A0 Datasheet - Page 81

• Manufacturer Part Number: LM3S2110-IQN20-A0
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0110.709F
November 29, 2007
Reset
Reset
Type
Type
Bit/Field
31:25
23:21
19:16
15:12
11:8
24
20
RO
RO
31
15
0
0
Register 14: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: CANs, PWM,
ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the
maximum clock frequency and maximum ADC sample rate. The format of this register is consistent
with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control
register.
RO
RO
30
14
MINSYSDIV
0
1
MINSYSDIV
reserved
reserved
reserved
reserved
Name
CAN0
PWM
RO
RO
29
13
0
1
reserved
RO
RO
28
12
0
1
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
reserved
Reset
0x7
0
1
0
1
0
0
RO
RO
25
0
9
0
Preliminary
CAN0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Module Present
When set, indicates that the PWM module is present.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
RO
Value
0x7
24
1
8
0
Description
Specifies a 25-MHz clock with a PLL divider of 8.
MPU
RO
RO
23
0
7
1
reserved
RO
RO
22
0
6
0
reserved
RO
RO
21
0
5
0
PWM
PLL
RO
RO
20
1
4
1
LM3S2110 Microcontroller
WDT
RO
RO
19
0
3
1
SWO
RO
RO
18
0
2
1
reserved
SWD
RO
RO
17
0
1
1
JTAG
RO
RO
16
0
0
1
81