LM3S2110-IQN20-A0 Luminary Micro, Inc., LM3S2110-IQN20-A0 Datasheet - Page 15

• Manufacturer Part Number: LM3S2110-IQN20-A0
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Synchronous Serial Interface (SSI) ............................................................................................ 275
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Inter-Integrated Circuit (I
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
November 29, 2007
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 268
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 269
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 270
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 271
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 272
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 273
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 274
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 287
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 289
SSI Data (SSIDR), offset 0x008 ...................................................................................... 291
SSI Status (SSISR), offset 0x00C ................................................................................... 292
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 294
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 295
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 297
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 298
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 299
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 300
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 301
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 302
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 303
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 304
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 305
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 306
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 307
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 308
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 309
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 310
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 311
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 326
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 327
C Master Data (I2CMDR), offset 0x008 ......................................................................... 331
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 332
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 333
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 334
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 335
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 336
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 337
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 339
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 340
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 342
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 343
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 344
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 345
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 346
2
C) Interface ........................................................................................ 312
Preliminary
LM3S2110 Microcontroller
15