LM3S2110-IQN20-A0 Luminary Micro, Inc., LM3S2110-IQN20-A0 Datasheet - Page 14

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LM3S2110-IQN20-A0

Manufacturer Part Number
LM3S2110-IQN20-A0
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
Table of Contents
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Watchdog Timer ........................................................................................................................... 211
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 234
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
14
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 203
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 204
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 205
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 206
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 207
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 208
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 209
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 210
Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 214
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 215
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 216
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 217
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 218
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 219
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 220
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 221
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 222
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 223
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 224
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 225
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 226
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 227
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 228
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 229
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 230
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 231
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 232
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 233
UART Data (UARTDR), offset 0x000 ............................................................................... 242
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 244
UART Flag (UARTFR), offset 0x018 ................................................................................ 246
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 248
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 249
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 250
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 251
UART Control (UARTCTL), offset 0x030 ......................................................................... 253
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 255
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 257
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 259
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 260
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 261
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 263
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 264
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 265
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 266
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 267
Preliminary
November 29, 2007

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