LM3S2110-IQN20-A0 Luminary Micro, Inc., LM3S2110-IQN20-A0 Datasheet - Page 39

• Manufacturer Part Number: LM3S2110-IQN20-A0
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

3
Table 3-1. Memory Map
November 29, 2007
Start
Memory
0x0000.0000
0x2000.0000
0x2010.0000
0x2200.0000
0x2400.0000
FiRM Peripherals
0x4000.0000
0x4000.4000
0x4000.5000
0x4000.6000
0x4000.7000
0x4000.8000
0x4000.C000
Peripherals
0x4002.0000
0x4002.0800
0x4002.4000
0x4002.5000
0x4002.6000
0x4002.7000
0x4002.8000
0x4003.0000
0x4003.1000
0x4003.2000
0x4003.C000
0x4004.0000
0x400F.D000
0x400F.E000
0x4200.0000
Private Peripheral Bus
Memory Map
The memory map for the LM3S2110 controller is provided in Table 3-1 on page 39.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Important:
In Table 3-1 on page 39, addresses not listed are reserved.
a
End
0x0000.FFFF
0x2000.3FFF
0x21FF.FFFF
0x23FF.FFFF
0x3FFF.FFFF
0x4000.0FFF
0x4000.4FFF
0x4000.5FFF
0x4000.6FFF
0x4000.7FFF
0x4000.8FFF
0x4000.CFFF
0x4002.07FF
0x4002.0FFF
0x4002.4FFF
0x4002.5FFF
0x4002.6FFF
0x4002.7FFF
0x4002.8FFF
0x4003.0FFF
0x4003.1FFF
0x4003.2FFF
0x4003.CFFF
0x4004.0FFF
0x400F.DFFF
0x400F.EFFF
0x43FF.FFFF
Description
On-chip flash
Bit-banded on-chip SRAM
Reserved non-bit-banded SRAM space
Bit-band alias of 0x2000.0000 through 0x200F.FFFF
Reserved non-bit-banded SRAM space
Watchdog timer
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
SSI0
UART0
I2C Master 0
I2C Slave 0
GPIO Port E
GPIO Port F
GPIO Port G
GPIO Port H
PWM
Timer0
Timer1
Timer2
Analog Comparators
CAN0 Controller
Flash control
System control
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
Preliminary
b
c
LM3S2110 Microcontroller
For details on
registers, see
page ...
114
114
-
110
-
213
140
140
140
140
286
241
325
338
140
140
140
140
407
186
186
186
388
360
114
61
-
39