LM3S2110-IQN20-A0 Luminary Micro, Inc., LM3S2110-IQN20-A0 Datasheet - Page 414

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LM3S2110-IQN20-A0

Manufacturer Part Number
LM3S2110-IQN20-A0
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
Pulse Width Modulator (PWM)
PWM Raw Interrupt Status (PWMRIS)
Base 0x4002.8000
Offset 0x018
Type RO, reset 0x0000.0000
414
Reset
Reset
Type
Type
Bit/Field
31:17
15:1
16
0
RO
RO
31
15
0
0
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection;
it must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see page 415).
The PWM generator interrupts simply reflect the status of the PWM generator; they are cleared via
the interrupt status register in the PWM generator block. Bits set to 1 indicate the events that are
active; a zero bit indicates that the event in question is not active.
RO
RO
30
14
0
0
IntPWM0
reserved
reserved
IntFault
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
26
10
0
0
Reset
0x00
0x00
0
0
RO
RO
25
0
9
0
Preliminary
reserved
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Interrupt Asserted
Indicates that the fault input has been asserted.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM0 Interrupt Asserted
Indicates that the PWM generator 0 block is asserting its interrupt.
RO
RO
24
0
8
0
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
November 29, 2007
RO
RO
18
0
2
0
RO
RO
17
0
1
0
IntPWM0
IntFault
RO
RO
16
0
0
0

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