LM3S2110-IQN20-A0 Luminary Micro, Inc., LM3S2110-IQN20-A0 Datasheet - Page 361

• Manufacturer Part Number: LM3S2110-IQN20-A0
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

CAN Control (CANCTL)
CAN0 base: 0x4004.0000
Offset 0x000
Type R/W, reset 0x0000.0001
November 29, 2007
Reset
Reset
Type
Type
Bit/Field
31:8
7
6
5
4
3
RO
RO
31
15
0
0
Register 1: CAN Control (CANCTL), offset 0x000
This control register initializes the module and enables test mode and interrupts.
The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting
or resetting INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT
has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11
consecutive High bits) before resuming normal operations. At the end of the bus-off recovery
sequence, the Error Management Counters are reset.
During the waiting time after INIT is reset, each time a sequence of 11 High bits has been monitored,
a Bit0Error code is written to the CANSTS status register, enabling the CPU to readily check
whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the proceeding
of the bus-off recovery sequence.
RO
RO
30
14
0
0
reserved
reserved
Name
CCE
DAR
Test
EIE
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
Type
27
11
R/W
R/W
R/W
R/W
0
0
RO
RO
RO
RO
26
10
0
0
0x0000
Reset
0
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Test Mode Enable
0: Normal Operation
1: Test Mode
Configuration Change Enable
0: Do not allow write access to the CANBIT register.
1: Allow write access to the CANBIT register if the INIT bit is 1.
Disable Automatic Retransmission
0: Auto retransmission of disturbed messages is enabled.
1: Auto retransmission is disabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Error Interrupt Enable
0: Disabled. No Error Status interrupt is generated.
1: Enabled. A change in the Boff or EWarn bits in the CANSTS register
generates an interrupt.
RO
RO
24
0
8
0
reserved
R/W
Test
RO
23
0
7
0
CCE
R/W
RO
22
0
6
0
DAR
R/W
RO
21
0
5
0
reserved
RO
RO
20
0
4
0
LM3S2110 Microcontroller
R/W
RO
EIE
19
0
3
0
R/W
SIE
RO
18
0
2
0
R/W
RO
17
IE
0
1
0
INIT
R/W
RO
16
0
0
1
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