IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 73

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

0xFFFF, and is automatically cleared after reading to re-start DIP-2 error
counter accumulation.
9.4.9 Common module block base 0x0800 registers
SPI-4 ingress bit alignment window register
(Block_base 0x0800 + Register_offset 0x00)
TABLE 110 - SPI-4 INGRESS BIT ALIGNMENT
WINDOW REGISTER (REGISTER_OFFSET 0x00)
0x0800 + Register_offset 0x00. The SPI-4 ingress bit alignment window register
has read and write access. The SPI-4 ingress bit alignment window register is
used in manual bit alignment procedures and it is recommended to leave the
W field at its initial value.
setting the time between bit alignment operations. The initial value gives one
million cycles per bit alignment adjustment opportunity.
SPI-4 ingress lane measure register (Block_base
0x0800 + Register_offset 0x01)
TABLE 111 - SPI-4 INGRESS LANE MEASURE
REGISTER (REGISTER_OFFSET 0x01)
0x0800 + Register_offset 0x01. The SPI-4 ingress lane measure register has
read and write access. SPI-4 ingress lane measure register is used in manual
bit alignment procedures and it is recommended to leave the SPI-4 ingress lane
measure register at its initial value.
4 ingress data lane alignment. The LANE field is intended for diagnostics only
and is not needed in normal operation.
when the LANE process is busy for manual lane assignment procedures. The
MEASURE_BUSY field is intended for diagnostics only and is not needed for
normal operation.
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
LANE
Reserved
MEASURE_BUSY
The SPI-4 ingress bit alignment window register is addressed from Block_base
W
The SPI-4 ingress lane measure register is addressed from Block_base
LANE The LANE field is used to manually control the measurement of SPI-
MEASURE_BUSY
Field
W
Field
The W field is used to set the width of the SPI-4 ingress window by
0=DATA0 lane selected for measurement
x=DATAx lane selected for measurement
15=DATA15 lane selected for measurement
16=CTL selected for measurement
17=Egress status 0 selected for measurement
18=Egress status 1 selected for measurement
19=Chip test feature not available for diagnostics
0=Normal operation
1=Lane process is busy
The MEASURE_BUSY field is used to observe
Bits
15:0
Bits
4:0
7:5
8
Length
Length
16
5
3
1
Initial Value
Initial Value
0xFFFF
0
0
0
73
SPI-4 ingress bit alignment counter register
(Block_base 0x0800 + Register_offset 0x02 – 0x0B)
TABLE 112 - SPI-4 INGRESS BIT ALIGNMENT
COUNTER REGISTER (0x02 to 0x0B)
read-only and contains the values of the bit alignment counters used for manual
lane alignment . The registers are intended for diagnostics only and are not needed in
normal operation.
SPI-4 ingress manual alignment phase/result
register (Block_base 0x0800 + Register_offset
0x0C – 0x1F)
TABLE 113 - SPI-4 INGRESS MANUAL ALIGNMENT
PHASE/RESULT REGISTER (0x0C to 0x1F)
0x0800 have read and write access. A SPI-4 ingress manual alignment phase/
result register is used to manually align the phase of the data lane, control lane,
status lanes, and a test lane corresponding to its register in turn and is intended
for diagnostics only and is not needed in normal operation. If the FORCE field
of Table 99, SPI-4 ingress bit alignment control register (register_offset 0x11)
is set to a logic one, manual phase alignment is enabled. If the FORCE field is
set to a logic zero, normal automatic phase alignment is enabled, and the result
can be viewed here. There are five center taps to choose from, plus two guard
taps on either side of the center, per data bit sampled. The oldest data sample
is at tap 8 ("right"), while the newest data sample is at tap 0 ("left"). Taps 0 and
1 are the left margin taps for tracking purposes, while taps 7 and 8 are the right
margin taps. A tap between 2 to 7 is initially selected in automatic mode. See
Figure 7-Data sampling diagram. Register 0x0C is used for lane DATA0.
I_DCLK. The four bits number the phases from 0 to 8, relative to the positively-
clocked bit.
I_DCLK. The four bits number the phases from 0 to 8, relative to the negatively-
clocked bit.
SPI-4 egress data lane timing register (Block_base
0x0800 + Register_offset 0x2A)
TABLE 114 - SPI -4 EGRESS DATA LANE TIMING
REGISTER (REGISTER_OFFSET 0x2A)
Register_offset 0x2A has read and write access. The SPI-4 egress data lane
timing register is used to manually align the phase of data lane n by adding from
0.1 clock cycle to 0.3 clock cycles of delay.
DTC0[1:0]
DTC1[1:0]
…
DTC15[1:0]
The SPI-4 ingress bit alignment counter registers at Block_base 0x0800 are
PHASE_ASSIGN
The SPI-4 ingress manual alignment phase/result registers at Block_base
PHASE_ASSIGN [3:0]
Used for selecting the bit phase corresponding to the rising clock edge of
PHASE_ASSIGN [7:4]
Used for selecting the bit phase corresponding to the falling clock edge of
The SPI-4 egress data lane timing register at Block_base 0x0800 +
Field
Field
C[n]
Field
Bits
Bits
9:0
7:0
31:30
Bits
1:0
3:2
INDUSTRIAL TEMPERATURE RANGE
..
Length
Length
Length
10
8
2
2
2
2
APRIL 10, 2006
Initial Value
Initial Value
Initial Value
0
0
0
0
0
0