IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 25

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

4.1 SPI-3 to SPI-4 datapath and flow control
One packet fragment processor module is associated with one SPI-3 ingress
interface. The packet fragment processor module connects to the SPI-4
interface.
port buffers. A packet fragment processor transfers complete packet fragments
from the SPI-3 ingress port buffers to memory segments previously reserved
on a per-LP basis in the buffer segment pool. The SPI-3 ingress port buffer
SPI-3 ingress PFP functions
SPI-3 ingress buffers and the microprocessor insert buffer. The PFP processes
SPI-3 ingress buffers in high priority and the insert buffer with low priority. The
PFP copies data into the buffer segment , requests new buffer segments, and
generates entries in the SPI4-egress queue.
SPI-3 ingress buffer processing
ingress buffer is not occupied the PFP processes the insert buffer.
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
Two packet fragment processor modules from SPI-3 to SPI-4 are provided.
Packet fragments from the SPI-3 ingress are received into the SPI-3 ingress
The packet fragment processor(PFP) receives status information about the
The PFP verifies whether a SPI-3 ingress buffer is occupied. If the SPI-3
SPI3 Ingress
uP
insert buffer
FIFO status
Figure 13. SPI-3 ingress to SPI-4 egress packet fragment processor
SPI3 ingress port
PMON & DIAG
buffers
buffer segment pool
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watermark and the per-LP free buffer segment threshold information is combined
to produce SPI-3 ingress FIFO status towards the attached device. Packets or
packet fragments received on one SPI-3 ingress logical port can be forwarded
to any one of:
mapping to a Link Identification number (LID).
Normal operation
copied into the SP-3 egress buffers of that same port. This is a test mode only,
as no non-loopback traffic can be transferred at this time.
forwarded to the LID process by the PFP.
that are directed towards the PMON&DIAG module are:
A logical port on the egress SPI-4 interface.
The microprocessor interface, using the capture buffer.
The connection on the logical port level is performed through an intermediate
In loopback mode, all of the SPI-3 ingress buffers of a physical SPI-3 port are
In non – loop back mode (normal operation) the SPI-3 ingress buffers are
The LID process generates a set of events for an associated LID. The events
•
•
•
SPI-3 fragment event (all fragments) with an associated length field
SPI-3 error tagged packet event (errored packets)
SPI-3 EOP event (all packets)
capture
buffer
SPI3 egress port
uP
buffers
egress PFP
Associated
INDUSTRIAL TEMPERATURE RANGE
redirect
buffers
SPI-3
6372 drw14
SPI4 Egress
FIFO status
APRIL 10, 2006