IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 61

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

Non critical LID associated capture table
(Block_base 0x0C00 + Register_offset 0x10-0x15)
TABLE 66 - NON CRITICAL LID ASSOCIATED
CAPTURE TABLE (REGISTER_OFFSET 0x10-0x15)
Register_Offset 0x10-0x15. The Non critical LID associated capture table is
used to determine the EVENT_TYPE of SPI-3 and SPI-4 per-LID or per-LP
interrupts. The EVENT_TYPE coding is used to indicate which event or events
are pertinent to the interrupt in the Table 64 - LID associated interrupt indication
register(0x0E). The Non critical LID associated capture table is used to
determine the EVENT, and multiple bits can be active at the same time. The Non
critical LID associated capture table is read-only.
SPI-3 to SPI-4 critical LID interrupt indication
registers (Block_base 0x0C00 + Register_offset
0x16-0x17)
TABLE 67 - SPI-3 TO SPI-4 CRITICAL LID INTER-
RUPT INDICATION REGISTERS
(REGISTER_OFFSET 0x16-0x17)
0x0C00 + Register_offset 0x10-0x15.
indication registers. An interrupt is generated when enabled by the enable flag
in the SPI-3 to SPI-4 critical LID interrupt enableregisters. A SPI-3 to SPI-4 critical
LID interrupt indication register has read and write access. An interrupt indication
is cleared by writing a logical one to the appropriate bit of a SPI-3 to SPI-4 critical
LID interrupt indication register. Only one kind of critical event is defined-buffer
overflow. Each bit of the LID field set to logical one indicates the presence of a
buffer overflow event. A summary indication of as to which of the two sources,
SPI-3 to SPI-4 or SPI-4 to SPI-3, is responsible for the critical interrupt is indicated
in the Table 71 Critical events source indication register (0x1E).
SPI-3 to SPI-4 critical LID interrupt enable regis-
ters (Block_base 0x0C00 + Register_offset 0x18-
0x19)
TABLE 68 - SPI-3 TO SPI-4 CRITICAL LID INTERRUPT
ENABLE REGISTERS (REGISTER_OFFSET 0x18-
0x19)
access. A SPI-3 to SPI-4 critical LID interrupt enable register bits enable the
corresponding bits in a SPI-3 to SPI-4 critical LID interrupt indication register.
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
Register
The Non critical LID associated capture table is at Block_Base 0x0C00 +
The SPI-3 to SPI-4 critical LID interrupt indication registers are at Block_Base
Critical events are captured per LID in the SPI-3 to SPI-4 critical LID interrupt
The SPI-3 to SPI-4 critical LID interrupt enable registers have read and write
Register
Register
0x00
0x01
0x02
0x03
0x04
0x05
0x16
0x17
0x18
0x19
Inactive ingress SPI-3 logical port event
SPI-3 ingress data parity error
SPI-4 illegal SOP sequence event
SPI-4 illegal EOP sequence event
SPI-3 illegal SOP sequence event
SPI-3 illegal EOP sequence event
LID[31:0]
LID[63:32]
LID[31:0]
LID[63:32]
Field
Field
EVENT_TYPE
Bits
31:0
31:0
Bits
31:0
31:0
Length
Length
32
32
32
32
Initial Value
Initial Value
LID (6 bits)
LID (6 bits)
LID (6 bits)
LID (6 bits)
LID (6 bits)
Associated
LP (8 bits)
0x00
0x00
0x00
0x00
field
61
SPI-4 to SPI-3 critical LID interrupt indication
registers (Block_base 0x0C00 + Register_offset
0x1A-0x1B)
TABLE 69 - SPI-4 TO SPI-3 CRITICAL LID INTERRUPT
INDICATION REGISTERS (REGISTER_OFFSET
0x1A-0x1B)
0x0C00 + Register_offset 0x1A-0x1B.
indication register. An interrupt is generated when enabled by the enable flag
in the SPI-4 to SPI-3 critical LID interrupt enableregister. The SPI-4 to SPI-3
critical LID interrupt indication registers have read and write access. An interrupt
indication is cleared by writing a logical one to the appropriate bit of a SPI-4 to
SPI-3 critical LID interrupt indication register. Only one kind of critical event is
defined-buffer overflow. Each bit of a LID field set to logical one indicates the
presence of a buffer overflow event. A summary indication of as to which of the
two sources, SPI-3 to SPI-4 or SPI-4 to SPI-3, is responsible for the critical
interrupt is indicated in the Table 71 Critical events source indication register
(0x1E).
SPI-4 to SPI-3 critical LID interrupt enable regis-
ters (Block_base 0x0C00 + Register_offset 0x1C-
0x1D)
TABLE 70 - SPI-4 TO SPI-3 CRITICAL LID INTER-
RUPT ENABLE REGISTERS (REGISTER_OFFSET
0x1C-0x1D)
access. The SPI-4 to SPI-3 critical LID interrupt enable register bits enable the
corresponding bits in the SPI-4 to SPI-3 critical LID interrupt indication registers.
Critical events source indication register
(Block_base 0x0C00 + Register_offset 0x1E)
TABLE 71 - CRITICAL EVENTS SOURCE INDICA-
TION REGISTER (REGISTER_OFFSET 0x1E)
SPI34_OVR reflects the logical OR result of all bits in the SPI-3 to SPI-4 critical
LID associated interrupt indication registers. Bit SPI43_OVR reflects the logical
OR result of all bits in the SPI-4 to SPI-3 critical LID interrupt indication registers.
The SPI-4 to SPI-3 critical LID interrupt indication registers are at Block_Base
Critical events are captured per LID in a SPI-4 to SPI-3 critical LID interrupt
The SPI-4 to SPI-3 critical LID interrupt enable registers have read and write
The bits in the Critical events source indication register are read only. Bit
Register
Register
SPI34_OVR
SPI43_OVR
Reserved
0x1C
0x1D
0x1A
0x1B
Field
LID[31:0]
LID[63:32]
LID[31:0]
LID[63:32]
Field
Field
Bits
31:2
INDUSTRIAL TEMPERATURE RANGE
0
1
Bits
31:0
31:0
Bits
31:0
31:0
Length
30
1
1
Length
Length
32
32
32
32
APRIL 10, 2006
Initial Value
Initial Value
Initial Value
0b0
0b0
0x0
0x00
0x00
0x00
0x00