IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 26

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

Erroneous operation
immediately flushed. A SPI-3 flush event is generated.
Store process
table is required for each of the SPI-3 logical ports. Refer to Table 49, SPI-3
ingress LP to LID Map.
process. The internal Packet_length variable is initialized. The copy process
is triggered.
process and the queue process.
Buffer segment request process
pool.
updated.
generated and directed towards the Table 61, Non LID associated event
counters (0x00 - 0x0B). The buffer data is not copied into the SPI3-4 buffer.
Copy process
parity error status is stored in the Pack_Err variable. The Packet_Length
variables and Seg_Length variables are updated. The queue and request
processes are triggered when the number of bytes in the buffer segment equals
the SPI-3 packet fragment size programmed for that physical interface, or an
EOP is reached.
Queue process
Packet length check
parameters in the ingress SPI-3 Port descriptor table. If the packet length is less
than the programmed field MIN_LENGTH a “SPI-3 too short packet event” is
generated. If the packet length is greater than the programmed field MAX_LENGTH
a “SPI-3 too long packet event” is generated. The events are directed towards
the Table 61, Non LID associated event counters (0x00 - 0x0B).
SPI-3 to SPI-4 buffer management
SPI-3 ingress port. A configurable part of this buffer segment pool is assigned
to buffers associated to each of the up to 64 LIDs. The buffer size for a LID can
be configured in multiples (M) of 256 bytes. Fewer LIDs allow larger buffers per
LID, conversely a large number of LIDs will require smaller buffers per LID.
Within this restriction, the buffer size of each LID can be further restricted as
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
SPI-3 ingress buffers marked with an address parity error are always
The process parameters are stored in a descriptor table. One entry in the
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A new buffer segment is requested for the logical port from the buffer segment
The request can be accepted or rejected by the buffer pool.
When accepted, the Current_Seg and current Seg_Length variables are
When rejected, the SPI-3 ingress buffer is flushed. An SPI-3 flush event is
Data is retrieved from the buffer and stored in the current segment. The data
The current segment is entered into the SPI-4 egress queue.
The length of the packet is compared to the MIN_LENGTH and MAX_LENGTH
A 128 KB SPI-3 to SPI-4 buffer segment pool is assigned to each physical
Fragments tagged with an EOP indication will trigger the packet length check
Fragments tagged with an SOP indication trigger the buffer segment request
Non marked (EOP or SOP) buffers are subject to the copy process.
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needed to control latency. Modifications of the buffer size allocated to a LID are
supported only when the logical port associated to the LID is disabled. Attempts
to allocate more memory than available will generate an allocation error event.
The indirect access module will discard the attempt.
Free buffer segment pool
Storage
pool of free buffer segments. The buffer segment pool keeps track of the number
of segments assigned to each LID and holds a list of free segments.
Buffer segment requests
segment pool for that SPI-3 ingress physical port by the SPI-3 ingress packet
fragment processor associated to that SPI-3 physical port. A request may be
accepted immediately or rejected. When the request is accepted a buffer
segment ID is returned immediately.
Buffer segment pool returned segments
module releases it. This allows the segment to be used once more by the SPI-
3 ingress.
SPI-4 egress queues
Normal operation
to the number of logical ports as defined by the static NR_LID configuration. One
entry in the queue corresponds to a packet or a packet fragment to be forwarded
to the SPI-4 egress interface.
SPI-3 ingress Backpressure
SPI-3 physical interface towards the SPI-3 ingress interface. The status signals
request to transfer more data on the logical port associated to the LID. The
available status is defined by the function (if free segments [LID] > Threshold,
status =available).
SPI-4 egress direction control
an associated SPI-3 egress port (SPI-3 port A to B, or port C to D, only), to the
SPI-4 egress port, or discarded. The selection is defined for each of the 64 LIDs
by the associated DIRECTION field in the Table 13, Direction code assignment.
TABLE 13 - DIRECTION CODE ASSIGNMENT
The buffer segment pool is divided into 508 segments. The device holds a
A new segment for a logical Link (LID) can be requested from the buffer
A buffer segment can be returned to the buffer segment pool when the egress
508 SPI-4 egress queue entries are provided. They are evenly allocated
The module directs status signals for each of the 64 LIDs associated with a
The SPI-4 egress traffic can be captured by the microprocessor, directed to
DIRECTION
00
01
10
11
SPI-4
Associated SPI-3
Capture to microprocessor
Discard
INDUSTRIAL TEMPERATURE RANGE
Path
APRIL 10, 2006