IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 21

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

SPI-4 egress status channel
Status channel bit alignment
for the data channel.
Status Channel Frame synchronization
IN_SYNCH.
frame, status clear and status freeze.
updates status.
HUNT state
VALIDATE state if a single frame is found accompanied by a single valid training
pattern. A frame is considered to be found if : 1) only one frame word is at the
beginning of a frame, 2) the calendar selection word, if enabled, is matched, and
3) the DIP-2 calculation matched the received DIP-2.
VALIDATE state
the DIP-2 is checked.
transition to the IN_SYNCH state. The number is defined by the E_INSYNC_THR
field in Table 104-SPI-4 egress configuration register_0 (Block_base 0x0700
+ Register_offset 0x00).
IN_SYNCH state
DIP-2 error event, each event will be captured and counted.
(Clear status in HUNT mode). The number is defined by the E_OUTSYNC_THR
field in Table 104-SPI-4 egress configuration register_0 (Block_base 0x0700
+ Register_offset 0x00).
HUNT mode. If less than twelve consecutive training patterns are received,
synch will not be lost, and status frame starts at the end of training.
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
The bit alignment algorithm for the status channel is the same as was described
The status channel frame module has 3 states: HUNT, VALIDATE and
In the HUNT state, the status channel frame module searches for status
In the VALIDATE state, the status channel frame module checks DIP-2.
In the IN_SYNCH state, the status channel frame module checks DIP-2, and
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In the validate state, based on the frame found while in the HUNT state,
If a single DIP-2 error is found, transition to the HUNT state.
After a number of consecutive DIP-2 calculations proves to be error free,
In the validate state, the training pattern is not checked.
In the IN_SYNCH state, training frame and status frame are checked.
DIP-2 is checked for status frame. Each mismatched DIP-2 will generate a
After a number of consecutive DIP-2 errors, transition to the HUNT state.
The reception of twelve consecutive training patterns forces a transition to
Twelve consecutive ‘11’ patterns force a transition to the HUNT state.
Status updating occurs without waiting for the end of a status frame.
In the HUNT state, per Link status is fixed to ‘satisfied’.
In HUNT state, the PFP searches frame continuously. It transitions to the
A= a number of consecutive error free DIP-2s received
B= a number of consecutive DIP-2 errors, in training,
port disabled, or reset
HUNT
Figure 9. SPI-4 egress status state diagram
21
Validate
Status channel de-skew
channel.
LVTTL or LVDS status channel option
status interface. A logic low enables the LVTTL status interface.
Data channel
Data transfer and training
egressed to the SPI-4 interface. The switch between data burst, IDLE, and
training must obey the following rules:
No status channel option
SPI-4 egress configuration register_0 (register_offset 0x00).
The LVDS status channel deskew uses the same algorithm as the as the data
The LVDS_STA pin selects the interface type. A logic high enables the LVDS
At any cycle, the contents on the interface can be one of the following:
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In the HUNT or the VALIDATE state, the training pattern is sent.
In the IN_SYNCH state, data from is taken from the buffer segments and
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Payload control word generation:
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Payload data word
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Once the NOSTAT bit is set, the status channel is ignored. Refer to Table 104,
Status in default value.
No DIP error check.
No status updating, the received status fixed to STARVING.
Data channel works same as in IN_SYNCH state.
Control word: Payload control word, or idle control word or training control
word.
Data word: Payload data word or training data word.
Send IDLE if no data to transmit
SOP must not occur less than 8 cycles apart.
periodic training after current transfer finished
Bit 15, Control word type=1
Bit [14:13] EOPS per [see Glossary: SPI-4]. If an error tag is in the
descriptor, abort.
Bit [12] SOP refer to [see Glossary: SPI-4]
Eight Bit Address. Mapping table defined in Table 101, SPI-4 egress LID
to LP map (256 entries)
DIP-4 bit refer to [see Glossary]
Bit order refer to [see Glossary: SPI-4]
If only one byte is valid, 8 LSB (B7 to B0) is set to 0x00.
A
IN_SYNCH
6372 drw10
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006