IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 57

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

an LP.
of the SPI-3 interface on a per-LP basis.
9.3.4 Block base 0x0700 registers
SPI-3 egress configuration register (Block_base
0x0700 + Register_offset 0x00)
TABLE 55 - SPI-3 EGRESS CONFIGURATION
REGISTER (REGISTER_OFFSET=0x00)
SPI-3 egress configuration registers have read and write access. A SPI-3
egress configuration registers is used to control the poll sequence length of a
SPI-3 egress interface when the SPI-3 interface is in Link mode. The SPI-3
egress configuration register is used to add two cycles to STX or EOP as
required to interface to the attached device.
poll sequence is from the LP associated with LID0 to the LP associated with the
LID for POLL_LENGTH - 1.
dummy STX cycles to the SPI-3 egress interface to meet the needs of an attached
device.
dummy EOP cycles to the SPI-3 egress interface to meet the needs of an attached
device.
SPI-4 ingress to SPI-3 egress flow control register
(Block_base 0x0700 + Register_offset 0x01)
TABLE 56 - SPI-4 INGRESS TO SPI-3 EGRESS FLOW
CONTROL REGISTER (REGISTER_OFFSET=0x01)
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
Reserved
STX_SPACING
EOP_SPACING
Reserved
CREDIT_EN
BURST_EN
LOOP_BACK
Reserved
POLL_LENGTH
ENABLE
BIT_REVERSAL This bit is used to reverse the bit ordering of each byte
There is one SPI-3 egress configuration register per SPI-3 interface. The
POLL_LENGTH Link layer poll sequence length when in Link mode. The
STX_SPACING This bit is used to enable or disable the adding of two
EOP_SPACING This bit is used to enable or disable the adding of two
Field
Field
0=LP disabled
1=LP enabled
0=Disable bit reversal for an LP
1=Enable bit reversal for an LP
0= No dummy STX cycles are added to the SPI-3 egress.
1= Two dummy STX cycles are added to the SPI-3 egress
0= No dummy EOP cycles are added to the SPI-3 egress.
1= Two dummy EOP cycles are added to the SPI-3 egress
This bit is used to enable or disable the connection of a LID to
31:10
Bits
Bits
31:3
5:0
7:6
8
9
0
1
2
Length
Length
22
29
6
2
1
1
1
1
1
Initial Value
Initial Value
0x00
0b0
0b0
0b0
0x0F
0b00
0x00
0b0
0b0
57
access. The bit fields of the SPI-4 ingress to SPI-3 egress flow control register
are described.
the attached SPI-3 device is interpreted as status or credit information as selected
by the CREDIT_EN bit in the SPI-4 ingress to SPI-3 egress flow control Register.
If the status mode is used, data will be egressed until the status is changed by
the attached SPI-3 device. If the credit mode is used, the SPI-3 egress will
transmit only one packet fragment and then wait for an update in the internal buffer
segment pool status before sending another packet fragment.
to an LP. When this feature is not enabled, only one burst per LP is allowed into
the SPI-3 egress buffers.
transferred to a SPI-3 egress buffers of the same port. This mode is useful for
off-line diagnostics.
SPI-3 egress test register (Block_base 0x0700 +
Register_offset 0x02)
TABLE 57 - SPI-3 EGRESS TEST REGISTER
(REGISTER_OFFSET=0x02)
parity error is introduced on the SPI-3 egress LP through the ADD_PAR_ERR
bit field. A single data parity error is introduced on the SPI-3 egress LP through
the DAT_PAR_ERR bit field. The LP affected by these two parity error bit fields
is enumerated in the PORT_ADDRESS field. The bit fields of SPI-3 egress test
register are described. The bit fields are automatically cleared following the
generation of the associated error.
3 egress LP through the ADD_PAR_ERR bit field. The LP affected by the
ADD_PAR_ERR bit field is enumerated in the PORT_ADDRESS field.
egress LP through the DAT_PAR_ERR bit field. The LP affected by the
DAT_PAR_ERR bit field is enumerated in the PORT_ADDRESS field.
and the DAT_PAR_ERR bit fields is enumerated in the PORT_ADDRESS field.
The value of the PORT_ADDRESS is set from 0x00 to 0xFF.
ADD_PAR_ERR
DAT_PAR_ERR
Reserved
PORT_ADDRESS
The SPI-4 ingress to SPI-3 egress flow control register has read and write
CREDIT_EN
BURST_EN
LOOP_BACK
The SPI-3 egress test register has read and write access. A single address
ADD_PAR_ERR
DAT_PAR_ERR
PORT_ADDRESS
Field
0=Status mode
1=Credit mode
0=Disable burst enable
1=Enable burst enable
0=Disable loopback
1=Enable loopback
0=No parity error introduced
1=Introduce a single address parity error on the SPI-3 egress LP
0=No parity error introduced
1=Introduce a single data parity error on the SPI-3 egress LP
CREDIT_EN The flow control information received from
Multiple Burst Enable allows more than one burst to be sent
In this mode the contents of a SPI-3 ingress are directly
A single address parity error is introduced on the SPI-
A single data parity error is introduced on the SPI-3
Bits
15:8
7:2
The LP affected by both the ADD_PAR_ERR
0
1
INDUSTRIAL TEMPERATURE RANGE
Length
1
1
8
6
Initial Value
APRIL 10, 2006
0x0F
0x00
0b0
0b0