IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 37

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

5. PERFORMANCE MONITOR AND
DIAGNOSTICS
5.1 Mode of operation
monitor captures events and accumulates error events and diagnostics data.
Some performance monitor accumulators are associated to a physical port,
some to a LID.
5.2 Counters
by the timebase event. The data accumulated during the previous time period
can be accessed by the indirect access scheme. The counters are cleared when
the timebase expires. All counters are saturating, and will not overflow.
5.2.1 LID associated event counters
and for each LID to/from the SPI-4 module.
It is defined as “bad” when the packet is tagged with an error.
(0x000-0x17F).
5.2.2 Non - LID associated event counters
interfaces.
offset in the indirect access space, and for the events recorded.
5.3 Captured events
If at least one event is captured in one of the interrupt indication registers, an active
PMON service request is directed towards the interrupt module.
5.3.1 Non LID associated events
associated interrupt indication register (Block_base 0x0C00 + Register_offset
0x00 to 0x0B). An interrupt is generated if the event is enabled by its enable
flag in the Table 63 - Non LID associated interrupt enable register(Block_base
0x0C00 + Register_offset 0x0D). The interrupt is cleared by writing a logical
one to the Table 62 - Non LID associated interrupt indication register (Block_base
0x0C00 + Register_offset 0x00 to 0x0B).
5.3.2 LID associated events
defined in Table 64 - LID-associated interrupt indication register(0x0E) and are
associated with the physical interface. Critical events are defined as buffer
overflows within the IDT88P8341 device in Table 67, SPI-3 to SPI-4 critical LID
interrupt indication registers (register_offset 0x16-0x17).
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
A performance monitor & diagnostics module is available. The performance
All events and diagnostics data are accumulated during an interval defined
A set of event counters is provided for each of the 64 LPs on the SPI-3 interface
A packet is delineated by an SOP and EOP on the SPI-3 / SPI-4 logical port.
All packets that are not “bad” are considered “good”.
For more information refer to Table 60 - LID associated event counters
A set of event counters is provided for the SPI-3 and the SPI-4 physical
Refer to Table 61, Non LID associated event counters (0x00-0x0B) for the
Two categories of events are captured: LID and non LID associated events.
Non LID associated events are captured into the Table 62 - Non LID
Two types of LID associated events are captured. Non critical events are
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5.3.2.1 Non critical events
associated interrupt indication register(0x0E). An interrupt is generated if the
interrupt is enabled by its enable flag in the Table 65, LID-associated interrupt
enable register(0x0F). The interrupt indication is cleared by writing a logical one
to the Table 64, LID associated interrupt indication register(0x0E).
captured in Table 66, Non-critical LID associated capture table (0x10-0x15).
The table records the latest captured LID or LP.
5.3.2.2 Critical events
interrupt indication registers (Block_base 0x0C00 + Register_offset 0x16-
0x17) and Table 69, SPI-4 to SPI-3 critical LID interrupt indication registers
(0x1A-0x1B). An interrupt is generated if enabled by the corresponding enable
flag in the Table 68, SPI-3 to SPI-4 critical LID interrupt enable registers (0x18-
0x19) and Table 70, SPI-4 to SPI-3 critical LID interrupt enable registers (0x1C-
0x1D). The indication is cleared by writing a logical one to the Table 67, SPI-
3 to SPI-4 critical LID interrupt indication registers (0x16-0x17) or Table 69, SPI-
4 to SPI-3 critical LID interrupt indication registers (0x1A-0x1B). Only one kind
of critical event is defined, buffer overflow. Since there are 64 x 2=128 critical
LID associated event sources, two source indication bits are contained in Table
71, Critical events source indication register (0x1E). The bits are read only. Bit
SPI34_OVR reflects the OR result of all bits in Table 67, SPI-3 to SPI-4 critical
LID interrupt indication registers (0x16-0x17). Bit SPI43_OVR reflects the OR
result of all bits in Table 69, SPI-4 to SPI-3 critical LID interrupt indication registers
(0x1A-0x1B).
5.3.3 Timebase
be configured to be internally or externally generated. A snapshot of the
counters is taken when the timebase expires and the counters are cleared. The
snapshot registers are accessed by an indirect access scheme.
5.3.3.1 Internally generated timebase
defined in Table 120, Timebase register (Register_offset 0x01). The configu-
ration specifies the number of master clock (MCLK) cycles required for each
period. For a description of MCLK refer to Chapter 6 Clock generator. The
timebase event is captured by the timebase status in Table 45, Secondary
interrupt status register (0x2D in the direct accessed space).
running timer input. The selection is made by the TIMER flag in the Table 119,
PMON update control register (Register_offset 0x00). When the time interval
expires, the TIMEBASE pin is asserted for sixteen MCLK cycles.
5.3.3.2 Externally generated timebase
A positive edge detector generates the timebase event. The timebase event is
captured by the timebase status in the Table 45 - Secondary interrupt status
register (0x2D in the direct accessed space).
LID associated non critical events are captured in the Table 64, LID-
When the event is captured, the LID or LP associated with the event is
Critical events are captured per LID in Table 67, SPI-3 to SPI-4 critical LID
A single timebase module is provided in the device. The timebase period can
The period of the timebase is configured for the device using the register
The internal timebase is generated either by the microprocessor or by a free
The externally generated timebase signal is applied on the TIMEBASE pin.
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006