IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 47

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

TABLE 24 - INDIRECT ACCESS BLOCK BASES FOR COMMON MODULE
Register offset
register offset is referred to as, “Register_offset”, in this document. A register
reference takes the form of, “[Register_offset 0xHH]”, where HH is the
hexadecimal value of the register offset.
Indirect register access
Indirect register write access
indirect access control register, and then writing data into the indirect access data
registers. Next, the address is written into the indirect access address registers.
Then, 0x00 is written into the indirect access control register. The status of the
IND_BUSY flag in the indirect access control register is checked to ensure the
process has completed before another indirect access can be initiated.
TABLE 25 - INDIRECT ACCESS DATA REGISTERS
(DIRECT ACCESSED SPACE) AT 0x30 to 0x33
TABLE 26 - INDIRECT ACCESS ADDRESS REGISTER
(DIRECT ACCESSED SPACE) AT 0x34 to 0x35
TABLE 27 - INDIRECT ACCESS CONTROL REGISTER
(DIRECT ACCESSED SPACE) AT 0x3F
The fields for this register are defined below.
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
ADDRESS[7:0]
ADDRESS[15:8]
ERROR code
R/WN
IND_BUSY
Block_base
The register offset is shown in the section where the register is defined. The
An indirect write access is initiated by first checking for IND_BUSY=0 in the
0x0000
0x0100
0x0200
0x0300
0x0400
0x0500
0x0600
0x0700
0x0800
0x0900
Field
Field
Field
SPI-4 ingress LP to LID tables
SPI-4 ingress calendar_0
SPI-4 ingress calendar_1
SPI-4 ingress registers
SPI-4 egress LID to LP map
SPI-4 egress calendar_0
SPI-4 egress calendar_1
SPI-4 egress configuration and status registers
SPI-4 ingress timing block registers
PMON timebase control, clock generator control, GPIO register, and version number
7:0
15:8
23:16
31:24
7:0
15:8
5:0
6
7
Bits
Bits
Bits
Length
Length
Length
8
8
8
8
8
8
6
1
1
Indirect Data Register 0x30
Indirect Data Register 0x31
Indirect Data Register 0x32
Indirect Data Register 0x33
Indirect Low Address Register 0x34
Indirect High Address Register 0x35
Function
Function
Function
47
Indirect register read access
indirect access control register, and then writing the address into the indirect
access address registers. Then, 0x40 is written into the indirect access control
register. The status of the IND_BUSY flag in the indirect access control register
is checked to ensure the process has completed, and then data is read out from
the indirect access data registers.
registers for controlling indirect register access are directly accessible with read
and write access.
An indirect read access is initiated by first checking for IND_BUSY=0 in the
The registers for controlling indirect register access are shown below. The
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006