IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet
IDT88P8341
Available stocks
Related parts for IDT88P8341
IDT88P8341 Summary of contents
Page 1
... IP services equipment DESCRIPTION The IDT88P8341 is a SPI (System Packet Interface) Exchange with a SPI- 3 interface and a SPI-4 interface. The data that enter on the low speed interface (SPI-3) are mapped to logical identifiers (LIDs) and enqueued for transmission over the high speed interface (SPI-4). The data that enter on the high speed interface (SPI-4) are mapped to logical identifiers (LIDs) and enqueued for transmission over the low speed interface (SPI-3) ...
Page 2
... Chip configuration sequence ................................................................................................................................................................. 40 8.2.2 Logical Port activation and deactivation .................................................................................................................................................. 41 8.2.3 Buffer segment modification .................................................................................................................................................................... 41 8.2.4 Manual SPI-4 ingress LVDS bit alignment .............................................................................................................................................. 41 8.2.5 SPI-4 status channel software ............................................................................................................................................................... 42 8.2.6 IDT88P8341 layout guidelines .............................................................................................................................................................. 42 8.2.7 Software Eye-Opening Check on SPI-4 Interface .................................................................................................................................. 43 9. Register description .............................................................................................................................................................................................. 45 9.1 Register access summary ................................................................................................................................................................................ 45 9.1.1 Direct register format ............................................................................................................................................................................. 45 9.1.2 Indirect register format ........................................................................................................................................................................... 45 9 ...
Page 3
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Table of Contents (Continued) 9.3 Indirect registers for SPI-3A module .................................................................................................................................................................. 54 9.3.1 Block base 0x0000 registers ................................................................................................................................................................. 55 9.3.2 Block base 0x0200 registers ................................................................................................................................................................. 55 9.3.3 Block base 0x0500 registers ................................................................................................................................................................. 56 9.3.4 Block base 0x0700 registers ................................................................................................................................................................. 57 9.3.5 Block base 0x0A00 registers ................................................................................................................................................................. 59 9.3.6 Block base 0x0C00 registers ................................................................................................................................................................. 59 9.3.7 Block base 0x0100 registers ................................................................................................................................................................. 62 9 ...
Page 4
... Figure 38. Microprocessor parallel port Intel mode read timing diagram .......................................................................................................................... 85 Figure 39. Microprocessor parallel port Intel mode write timing diagram .......................................................................................................................... 86 Figure 40. Microprocessor serial peripheral interface timing diagram .............................................................................................................................. 87 Figure 41. IDT88P8341 820PBGA package, bottom view .............................................................................................................................................. 92 Figure 42. IDT88P8341 820PBGA package, top and side views .................................................................................................................................... 93 List of Figures 4 INDUSTRIAL TEMPERATURE RANGE ...
Page 5
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Table 1 – I/O types .......................................................................................................................................................................................................... 9 Table 2 – SPI-3 ingress interface pin definition .................................................................................................................................................................. 9 Table 3 – SPI-3 egress interface pin definition ................................................................................................................................................................ 10 Table 4 – SPI-3 status interface pin definition .................................................................................................................................................................. 10 Table 5 – SPI-4 ingress interface definition ..................................................................................................................................................................... 11 Table 6 – SPI-4 egress interface definition ...................................................................................................................................................................... 11 Table 7 – ...
Page 6
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 List of Tables (Continued) Table 57 - SPI-3 egress test register (register_offset=0x02) ............................................................................................................................................ 57 Table 58 - SPI-3 egress fill level register (register_offset=0x03) ...................................................................................................................................... 58 Table 59 - SPI-3 egress max fill level register (register_offset=0x04) .............................................................................................................................. 58 Table 60 - LID associated event counters (0x000-0x17F) .............................................................................................................................................. 59 Table 61 - Non LID associated event counters (0x00 - 0x0B) ........................................................................................................................................ 59 Table 62 - Non LID associated interrupt indication register (register_offset 0x0c) ...
Page 7
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 List of Tables (Continued) Table 112 - SPI-4 ingress bit alignment counter register (0x02 to 0x0B) ......................................................................................................................... 73 Table 113 - SPI-4 ingress manual alignment phase/result register (0x0C to 0x1F) .......................................................................................................... 73 Table 114 - SPI -4 egress data lane timing register (register_offset 0x2A) ....................................................................................................................... 73 Table 115 - SPI-4 egress Control Lane Timing register (Register_offset 0x2B) ............................................................................................................... 74 Table 116 - SPI-4 egress data clock timing register (register_offset 0x2C) ...
Page 8
... Framer Figure 1. Typical application: optical port and NPU/Traffic Manager 1. INTRODUCTION The IDT88P8341 device is a SPI-3 to SPI-4 exchange intended for use in optical line cards, Ethernet transport, and multi-service switches. The SPI- 3 and SPI-4 interfaces are defined by the Optical Interworking Forum. The device can be used as a rate adapter, a switch aggregation device between network processor units, multi-gigabit framers and PHYs, and switch fabric interface devices ...
Page 9
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 2. PIN DESCRIPTION SPI-3 For the SPI-3 interface, each pin is used differently depending whether the SPI Link mode or in PHY mode. The SPI-3 interface is configurable for either Link or PHY mode. This configuration pertains to both the ingress and egress paths ...
Page 10
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 TABLE 3 – SPI-3 EGRESS INTERFACE PIN DEFINITION Generic Name Specific Name E_FCLK SPI3A_E_FCLK E_ENB SPI3A_E_ENB E_DAT[31:0] SPI3A_E_DAT[31:0] E_MOD[1:0] SPI3A_E_MOD[1:0] E_PRTY SPI3A_E_PRTY E_SOP SPI3A_E_SOP E_EOP SPI3A_E_EOP E_ERR SPI3A_E_ERR E_SX SPI3A_E_SX TABLE 4 – SPI-3 STATUS INTERFACE PIN DEFINITION ...
Page 11
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 SPI-4 For the SPI-4 interface, each pin is used differently depending whether the SPI Link mode or in PHY mode. The pin is given a generic name, shown TABLE 5 – SPI-4 INGRESS INTERFACE DEFINITION Generic Name Specific Name I_DCLK (P & N) SPI4_I_DCLK_P ...
Page 12
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Parallel microprocessor Interface The Parallel microprocessor interface is configurable to work in Intel or Motorola modes. Be sure to connect SPI_EN to a logic low when using the parallel microprocessor interface mode. TABLE 7 – PARALLEL MICROPROCESSOR INTERFACE Name I/O type MPM I-PU CMOS Microprocessor mode: 0=Motorola Mode, 1=Intel mode (sampled after reset) CSB I-ST CMOS Chip select ...
Page 13
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 3. EXTERNAL INTERFACES The external interfaces provided on the IDT88P8341 device are two SPI- 3 interfaces, one SPI-4 interface, a serial or parallel microprocessor interface, a JTAG interface, and a set of GPIO pins. Each of the interfaces is defined in the relevant standard. The following information contains a set of the highlights of the features supported from the relevant standards, and a description of additional features implemented to enhance the usability of these interfaces for the system architect ...
Page 14
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 SPI-3 ingress Link mode Refer to [Glossary] for details about the SPI-3 interface. • The PHY pushes data into the device in blocks from 256 bytes. • The SPI Exchange provides backpressure for the SPI-3 ingress physical interface by the I_ENB signal ...
Page 15
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 3.1.2 SPI-3 egress - All fragments will programmable equal length with the exception of EOP fragment which may be shorter LID to LP map - 64 entries, one per LID, for each SPI-3 egress port - LP enable control Multiple burst enable - Allows more than one burst to be sent to an LP. ...
Page 16
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 SPI-3 egress Link mode The SPI Exchange receives status information from the PHY. The PHY indicates its ability to receive data. Status information for all logical ports is directed towards the packet fragment processor. Status information is received from the PHY. ...
Page 17
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 3.2 SPI-4 Refer to OIF SPI-4 document (see Glossary) for full details of the implemen- tation agreement. - Clock rate 400 MHz (160 - 800MHz DDR) - Link and PHY modes supported - Address range 0 to 255 with support for 64 simultaneously active logical ...
Page 18
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Data sampling The I_LOW field in the Table 89 SPI-4 ingress configuration register (Block_base 0x0300 + Register_offset 0x00) selects an operating mode between 80 MHz and 200 MHz or between 200 MHz and 400 MHz. Each lane is over-sampled by a factor of five. The over-sampled data is ...
Page 19
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Manual phase selection The automatic phase adjustment can be overruled by the processor when the FORCE flag is set see Table 99, SPI-4 ingress bit alignment control register (register_offset 0x11). The PHASE_ASSIGN field see Table 113, SPI-4 ingress manual alignment phase/result register (0x0C to 0x1F) now defines the selected phase ...
Page 20
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 • Normal status information when in the IN_SYNCH state The normal status information is generated based on ingress buffer full information and PFP buffer segment fill level. For information on DIP-2 generation and training pattern refer to the OIF SPI- 4 document [Glossary]. ...
Page 21
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 SPI-4 egress status channel Status channel bit alignment The bit alignment algorithm for the status channel is the same as was described for the data channel. Status Channel Frame synchronization A= a number of consecutive error free DIP-2s received B= a number of consecutive DIP-2 errors, in training, The status channel frame module has 3 states: HUNT, VALIDATE and IN_SYNCH ...
Page 22
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 3.3 Microprocessor interface - Parallel microprocessor interface • 8 bit data bus for parallel operation • Byte access • Direct accessed space • Indirect access space is used for most registers • Read operations to a reserved address or reserved bit fields return 0 • ...
Page 23
... SPI-4 <-> microprocessor interface Where <-> indicates a bidirectional data path. The IDT88P8341 supports one SPI-3 interface and one SPI-4 interface. The SPI-3 interface can operate in a PHY or Link mode. Refer to Figure 11, Definition of Data Flows for the main data flows in the device. Logical data flows are transported over the physical ports ...
Page 24
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 DATAPATH CONFIGURATION A logical view of datapath configuration using Packet Fragment Processors is shown in Figure 12, Logical View of Datapath Configuration Using PFPs. Two PFPs are associated with each SPI-3 port, one for ingress and one for SPI-3 INGRESS DATA LID ...
Page 25
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 4.1 SPI-3 to SPI-4 datapath and flow control Two packet fragment processor modules from SPI-3 to SPI-4 are provided. One packet fragment processor module is associated with one SPI-3 ingress interface. The packet fragment processor module connects to the SPI-4 interface. ...
Page 26
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Erroneous operation SPI-3 ingress buffers marked with an address parity error are always immediately flushed. A SPI-3 flush event is generated. Store process The process parameters are stored in a descriptor table. One entry in the table is required for each of the SPI-3 logical ports. Refer to Table 49, SPI-3 ingress LP to LID Map. • ...
Page 27
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 SPI-4 egress data bursts The PFP produces fragments N*16 bytes defined by the MAX_BURST_H or MAX_BURST_S parameter associated with each LID. For a high priority (starving) LID the MAX_BURST_S parameter is used. For a low priority (hungry) LID the MAX_BURST_H parameter is used. The PFP may ...
Page 28
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 SPI-4 egress interface port associated control The SPI-4 interface has an associated LID to LP map (See Table 101 - SPI- 4 egress LID to LP Map Block_base 0x0400 = Register_offset 0x00 - 0xFF) for the purpose of directing the packet fragments from the selected SPI-3 ingress main memory buffer segment pool to the SPI-4 egress interface ...
Page 29
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 SPI-3 ingress to SPI-4 egress flow control For control information there are two separate cases to consider: The case that the SPI-3 physical interface port is configured in Link mode, and the case that the SPI-3 is configured in PHY mode. Note that since the SPI-3 physical ...
Page 30
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 4.2 SPI-4 to SPI-3 datapath and flow control Two Packet Fragment Processor modules from SPI4 ingress to SPI-3 egress are provided, all connected to one SPI-4 ingress interface. Packet bursts from the SPI-4 ingress are received into the SPI-4 ingress port buffers ...
Page 31
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 SPI-4 ingress interface configurable parameters: The IDT88P8341 can interface to either a Link or a PHY layer device. The SPI-4 port can be enabled or disabled. The SPI-4 ingress bits are aligned with the ingress clock. In addition, the SPI- 4 words are then aligned among each other to produce valid words. This is performed both on the data channel and the status channel ...
Page 32
... The SPI-4 control information is transmitted to the adjacent device. The adjacent device determines which LP to service next according to the status information it receives from the IDT88P8341. The SPI-4 ingress data arrive in bursts that are of equal length except for the last burst of a packet which may be shorter ...
Page 33
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 4.3 Microprocessor interface to SPI-3 datapath capture/insert configurable parameters Enable insertion / capture of data to the SPI-3 or SPI-4 data stream (which is dependent on the egress control register). For each direction, the following are to be used: - Data for insertion or data captured - Data available: set when data is available. Asserted by device for capture, asserted by microprocessor for insertion ...
Page 34
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 4.3.2 Microprocessor insert to SPI-3 egress datapath The diagram below shows the datapath through the device from the microprocessor data insert interface to a SPI-3 egress port. The following is a description of the path taken by a fragment of data through the device. ...
Page 35
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 4.3.3 Microprocessor interface to SPI-4 egress datapath Packets can be inserted into the SPI-3-4 datapath by the microprocessor. The following is a description of the path taken by a burst of data through the device. Data and control information are written to the insert buffer through the microprocessor interface ...
Page 36
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 4.3.4 SPI-4 ingress to microprocessor interface datapath The diagram below shows the datapath through the device from the SPI-4 interface to the microprocessor data capture interface. The following is a description of the path taken by a burst of data through the device. ...
Page 37
... Two types of LID associated events are captured. Non critical events are defined in Table 64 - LID-associated interrupt indication register(0x0E) and are associated with the physical interface. Critical events are defined as buffer overflows within the IDT88P8341 device in Table 67, SPI-3 to SPI-4 critical LID interrupt indication registers (register_offset 0x16-0x17). INDUSTRIAL TEMPERATURE RANGE 5 ...
Page 38
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 6. CLOCK GENERATOR The device generates clocks from the SPI-4 ingress clock (I_DCLK) or from the REF_CLK input pin. The clock so selected is used for core functions of the device, and must be present during reset and thereafter. The selection and frequency divisors are defined by CK_SEL[3:0] pins as defined in the following Table 14, CK_SEL[3:0] input pin encoding ...
Page 39
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 7. LOOPBACKS Local loopbacks are supported of the SPI-3 physical port. The SPI-3 physical loopback is described below. SPI-3 8 bit / 32 bit Min: 19.44MHz Max: 133MHz 7.1 SPI-3 Loopback A SPI-3 physical port loop back is supported on the SPI-3 interface. In this mode, the contents of the SPI-3 ingress buffers are directly transferred to the SPI-3 egress buffers ...
Page 40
... T 1 Figure 31. Power-on-Reset Sequence 8.2 Software operation 8.2.1 Chip configuration sequence For proper device operation important to initialize the IDT88P8341 in the correct sequence following reset. This sequence is outlined in the following paragraphs. 1) Reset the IDT88P8341 chip. After reset, the chip will perform auto initialization ...
Page 41
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 2) Configure the clock generator as follows: a) Configure the value for the MCLK divider, OCLK dividers and enables in the Clock Generator Control Register (refer to Table 121, Clock generator control register (Register_offset 0x10)). b) Configure the values for I_LOW and E_LOW (refer to Table 89, SPI- 4 ingress configuration register (0x00) and Table 104, SPI-4 egress configuration register_0 (Register_offset 0x00) ...
Page 42
... Ensure a few nanoseconds of clock delay between one SPI-3 clock net and other SPI-3 clock nets of the same frequency to minimize simultaneous switching noise. The IDT88P8341 OCLK[3:0] outputs have skew between each output already built in, and so are useful in lowering simultaneous switching noise. A SPI-3 clock net is defined to be the SPI-3 egress clock for a device and the SPI-3 ingress clock for the attached device ...
Page 43
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 example, a SPI-4 clock of 400 MHz gives a data unit interval of 1.25 ns, so match the lengths within the entire signal group to within 625 ps inches. 3) Keep P and N signals within a differential pair on the same layer with the minimum trace spacing possible while still being able to get 100 ohms differential impedance (tightly edge-coupled pair routing) ...
Page 44
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 For an ideal case, there is zero jitter on clock an data, zero skew, the clock high and low level phase are symmetrical. For random input data on each lane, the counters Cn=CNTn(t)+CNTn(t+1)+. . .+CNTn(t+T), where time window to do the statistics computation, will increment as follows: ...
Page 45
... There are only a limited number of direct access registers due to the six address lines used on the IDT88P8341. All direct access registers are one byte wide. Most registers within the IDT88P8341 are of the indirect access type ...
Page 46
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 TABLE 20 - BIT ORDER WITHIN A 16-BIT ADDRESS REGISTER Indirect High Address (register 0x35) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Bit 15 is the most significant data bit. TABLE 21 - BIT ORDER WITHIN AN 8-BIT CONTROL REGISTER Indirect Control (register 0x3F) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0 Bit 7 is the most significant data bit ...
Page 47
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 TABLE 24 - INDIRECT ACCESS BLOCK BASES FOR COMMON MODULE Block_base 0x0000 SPI-4 ingress LP to LID tables 0x0100 SPI-4 ingress calendar_0 0x0200 SPI-4 ingress calendar_1 0x0300 SPI-4 ingress registers 0x0400 SPI-4 egress LID to LP map 0x0500 SPI-4 egress calendar_0 ...
Page 48
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 ERROR code Error code: see Error coding table. This error code pertains to the last indirect access attempted. TABLE 28 - ERROR CODING TABLE ERROR code Error Meaning 0x00 Normal indirect access completion 0x01 Multiple LP to same LID attempted assignment ...
Page 49
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 9.2 Direct access registers The direct access registers are in the directly-addressed access space. TABLE 29 - DIRECT MAPPED MODULE A REGISTERS Module A SPI-3 data capture control register SPI-3 data capture register SPI-4 data insert control register SPI-4 data insert register ...
Page 50
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 SPI-4 data insert control register TABLE 33 - SPI-4 DATA INSERT CONTROL REGISTER (REGISTER 0x02) Field Bits Length DATA_AVAILABLE 0 Reserved 7:1 The SPI-4 data insert control register has read and write access in the direct register access space. The microprocessor uses these registers to insert data into the SPI-3 ingress ...
Page 51
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Software reset TABLE 39 - SOFTWARE RESET REGISTER (0x20 in the direct accessed space) Field Bits Length SW_RESET 0 1 INIT_DONE 1 1 Reserved 7:2 6 The software reset bit is writable from the direct accessed memory space. Write a “1” to the SW_RESET bit to initiate the software reset. The SW_RESET bit will clear to a “ ...
Page 52
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 I_BUS_ERR_EN SPI-4 ingress bus error interrupt indication enable. 0=Disable bus error interrupt 1=Enable bus error interrupt SPI4_INACTIVE_TRANSFER_EN SPI-4 ingress inactive transfer inter- rupt indication enable. 0=Disable inactive transfer interrupt 1=Enable inactive transfer interrupt DCLK_UN_EN SPI-4 ingress data clock has transitioned from available to an unavailable condition interrupt indication enable ...
Page 53
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Primary interrupt status register (0x2C in the direct accessed space) TABLE 44 - PRIMARY INTERRUPT STATUS REGIS- TER (0x2C IN THE DIRECT ACCESSED SPACE) Field Bits MODULE_A 0 Reserved 1 Reserved 2 Reserved 3 SPI-4 4 SECONDARY 5 Reserved 7:6 The primary interrupt status register (0x2C in the direct accessed space) has read-only access ...
Page 54
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 9.3 Indirect registers for SPI-3A module Module Module_base 0x0000 TABLE 48 - MODULE A INDIRECT REGISTER Table Number, Page Block_base, Register_offset 49, page 54 0x0000, 0x00-0xFF 50, page 54 0x0200, 0x00 51, page 55 0x0200, 0x01 52, page 55 0x0200, 0x02 53, page 55 0x0200, 0x03 54, page 55 0x0500, 0x00-0x3F ...
Page 55
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 9.3.1 Block base 0x0000 registers SPI-3 ingress LP to LID map (Block_base 0x0000 + Register_offset 0x00 to 0xFF) TABLE 49 - SPI-3 INGRESS LP TO LID MAP Field Bits Length LID 5:0 6 ENABLE 6 1 BIT_REVERSAL 7 1 There are 256 SPI-3 ingress Logical Port (LP) to Logical Identifier (LID) registers, one per potential SPI-3 LP ...
Page 56
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 0=Odd parity on this port 1=Even parity on this port PARITY_EN The SPI-3 interface is provisioned to enable or disable parity generation and checking, according to the state of the EVEN_PARITY bit. 0=Disable parity on this SPI-3 port 1=Enable parity on this SPI-3 port WATERMARK The SPI-3 interface can be set to a SPI-3 ingress port watermark value ...
Page 57
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 ENABLE This bit is used to enable or disable the connection of a LID to an LP. 0=LP disabled 1=LP enabled BIT_REVERSAL This bit is used to reverse the bit ordering of each byte of the SPI-3 interface on a per-LP basis. 0=Disable bit reversal for an LP 1=Enable bit reversal for ...
Page 58
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 SPI-3 egress fill level register (Block_base 0x0700 + Register_offset 0x03) TABLE 58 - SPI-3 EGRESS FILL LEVEL REGISTER (REGISTER_OFFSET=0x03) Field Bits Length FILL_CUR 3:0 Reserved 4 E_FCLK_AV 5 There is one register for SPI-3 egress fill level register for the SPI-3 interface. The register has read-only access. The bit fields of the SPI-3 egress fill level register are described ...
Page 59
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Performance monitor counters Two categories of events are captured: LID and non LID associated events least one event is captured in one of the interrupt indication registers, an active PMON service request is directed towards the interrupt module. All events and diagnostics data are accumulated during an interval defined by the time base event ...
Page 60
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Non LID associated interrupt indication register (Block_base 0x0C00 + Register_offset 0x0C) TABLE 62 - NON LID ASSOCIATED INTERRUPT INDICATION REGISTER (REGISTER_OFFSET 0x0C) Field Bits Length SPI4_LOCK_UN 0 SPI3_LOCK_UN 1 SPI3_ICLK_UN 2 SPI3_ECLK_UN 3 SPI3_FLUSH 4 Reserved 31:5 The Non LID associated interrupt indication register is at Block_Base 0x0C00 ...
Page 61
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Non critical LID associated capture table (Block_base 0x0C00 + Register_offset 0x10-0x15) TABLE 66 - NON CRITICAL LID ASSOCIATED CAPTURE TABLE (REGISTER_OFFSET 0x10-0x15) Register EVENT_TYPE 0x00 Inactive ingress SPI-3 logical port event 0x01 SPI-3 ingress data parity error 0x02 SPI-4 illegal SOP sequence event ...
Page 62
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 9.3.7 Block base 0x0100 registers SPI-3 ingress packet length configuration register (Block_base 0x1000 + Register_offset 0x00-0x3F) TABLE 72 - SPI-3 INGRESS PACKET LENGTH CONFIGURATION REGISTER Field Bits Length MIN_LENGTH 7:0 Reserved 15:8 MAX_LENGTH 29:16 There is one set of SPI-3 ingress packet length configuration registers for the SPI-3 ingress interface ...
Page 63
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 FREE_SEGMENT The FREE_SEGMENT field is used to define the SPI- 3 ingress per-LID free segment backpressure threshold based on the number of free buffer segments (M) available, as follows: THRESHOLD = N * FREE_SEGEMENT, Where the value defined as a function of the domain of M: M[8:0] N (base 10) ...
Page 64
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 9.3.11 Block base 0x1600 registers The SPI-4 ingress registers are at Block_base 0x1600. SPI-4 ingress packet length configuration (Block_base 0x1600 + Register_offset 0x00-0x3F) TABLE 79 - SPI-4 INGRESS PACKET LENGTH CONFIGURATION (64 ENTRIES CONFIGURABLE) Field Bits Length MIN_LENGTH 7:0 Reserved 15:8 MAX_LENGTH 29:16 There is oneset of 64 registers for SPI-4 ingress packet length configuration associated with the SPI-3 interface ...
Page 65
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 9.3.14 Block base 0x1900 registers SPI-4 to SPI-3 PFP register (Block_base 0x1900 + Register_Offset 0x00) TABLE 83 - SPI-4 TO SPI-3 PFP REGISTER (0x00) Field Bits Length NR_LID 2:0 Reserved 7:3 The SPI-4 ingress to SPI-3 egress Packet Fragment Processor registers are at Block_Base 0x1900 + Register_offset 0x00. A SPI-4 to SPI-3 PFP Register has read and write access ...
Page 66
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 9.4 Common module indirect registers (Module_base 0x8000) TABLE 85 -COMMON MODULE (MODULE_BASE 0x8000) INDIRECT REGISTER TABLE Table Number, Page Block_base, Register_offset 86, page 66 0x0000, 0x00-0xFF 87, page 66 0x0100, 0x00-0xFF 88, page 66 0x0200, 0x00-0xFF 89, page 66 0x0300, 0x00 90, page 67 0x0300, 0x01 91, page 67 0x0300, 0x02 ...
Page 67
... OC-48 channels would benefit from more frequent FIFO status channel updates. The LP field values range from 0x00 to 0xFF. The IDT88P8341 and the attached device must have identical calendars for ingress and the attached egress device. The ingress and egress of the IDT88P8341 do not have to match, however. LP The LP value programmed schedules a status channel update according to the calendar sequence ...
Page 68
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 SPI-4_EN The SPI-4 ingress path is enabled using this field. The SPI-4 path is disabled during reset and while configuring the port, and then is enabled for normal use. 0=SPI-4 ingress is disabled 1= SPI-4 ingress is enabled I_CLK_EDGE The SPI-4 ingress LVTTL clock active clock edge is selected using the I_CLK_EDGE field ...
Page 69
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 SPI-4 ingress calendar configuration register (Block_base 0x0300 + Register_offset 0x04 - 0x05) TABLE 93 - SPI-4 INGRESS CALENDAR CONFIGU- RATION REGISTER (0x04 to 0x05) Field Bits Length I_CAL_M 7:0 I_CAL_LEN 13:8 The SPI-4 ingress calendar configuration registers are at Block_base 0x0300 and have read and write access. The Register_offset for calendar_0 is 0x04 ...
Page 70
... OC-12 channels, since the higher data rate of the OC-48 channels would benefit from more frequent FIFO status channel updates. The LP field values range from 0x00 to 0xFF. The IDT88P8341 and Initial Value the attached devices must have identical calendars. ...
Page 71
... SPI-4 could have OC-48 channels appear in the calendar at four times the rate of OC-12 channels, since the higher data rate of the OC-48 channels would benefit from more frequent FIFO status channel updates. The LP field values range from 0x00 to 0xFF. The IDT88P8341 and the attached devices must have identical calendars. LP The LP value programmed schedules a status channel update according to the calendar sequence ...
Page 72
... The bit fields of the SPI-4 egress calendar configuration register are described. The IDT88P8341 calendar length can be programmed to any multiple of 4 using suitable values for the calendar entries, calendar length and calendar M. If the adjacent device is unable to configure its calendar multiple of 4, conversion logic may be needed between the adjacent device SPI-4 status signals and the 88P8341 signals ...
Page 73
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 0xFFFF, and is automatically cleared after reading to re-start DIP-2 error counter accumulation. 9.4.9 Common module block base 0x0800 registers SPI-4 ingress bit alignment window register (Block_base 0x0800 + Register_offset 0x00) TABLE 110 - SPI-4 INGRESS BIT ALIGNMENT WINDOW REGISTER (REGISTER_OFFSET 0x00) ...
Page 74
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 DTCn [1:0] Used for adding 0.1 clock cycles of output delay to SPI- 4 egress data lane n. [1:0]=0=No added delay [1:0]=1=Add 0.1 clock cycle of delay to data lane n [1:0]=2=Add 0.2 clock cycles of delay to data lane n [1:0]=3=Add 0.3 clock cycles of delay to data lane n SPI-4 egress control lane timing register ...
Page 75
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 9.4.10 Common module block base 0x0900 registers PMON timebase control register (Block_base 0x0900 + Register_offset 0x00) TABLE 119 - PMON TIMEBASE CONTROL REGIS- TER (REGISTER_OFFSET 0x00) Field Bits Length INTERNAL 0 TIMER 1 MANUAL 2 A single PMON timebase module is available in the IDT88P8344. The PMON timebase module directs a timebase event to all PMON modules in the device ...
Page 76
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 General purpose I/O (Block_base 0x0900 + Register_offset 0x20) TABLE 123 - GPIO REGISTER (REGISTER_OFFSET 0x20) Field Bits Length DIR_OUT 4:0 Reserved 7:5 LEVEL 12:8 Reserved 15:13 MONITOR_EN 20:16 Five general purpose I/O pins are provided. Each pin I/O direction is controlled by the DIR_OUT field in the GPIO register. The logical level on a GPIO pin is controlled by the LEVEL field in the GPIO register if DIR_OUT=1 (pin=output), or sensed if DIR_OUT=0 (pin=input) ...
Page 77
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 10. JTAG INTERFACE The device supports the optional TRST input signal. It supports a TCK clock frequency up to 10MHz. TABLE 126 – JTAG INSTRUCTIONS Code Instruction 000 EXTEST 001 IDCODE 010 SAMPLE 011 CLAMP 100 HIGHZ 101 Private 111 ...
Page 78
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 11.3 Terminal Capacitance TABLE 129 – TERMINAL CAPACITANCE Parameter Symbol Input Capacitance C I Load Capacitance C O Load Capacitance for OCLK C O [3:0] signals Load Capacitance for C O microprocessor interface 11.4 Thermal Characteristics TABLE 130 – THERMAL CHARACTERISTICS Parameter Typical Power Dissipation total Typical Power Dissipation from 1 ...
Page 79
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 11.5 DC Electrical characteristics TABLE 131 – DC ELECTRICAL CHARACTERISTICS Parameter Description CMOS I/O V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH V RESETB Reset Input High Voltage RESETBH V RESETB Reset Input Low Voltage ...
Page 80
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 11.6 AC characteristics 11.6.1 SPI-3 I/O timing Refer to [SPI-3 in Glossary] for logical timing diagrams of the SPI-3 and SPI- 4 interfaces. Note that underclocking and overclocking for the SPI-4 and SPI- 3 interfaces is supported. I_F C LK SPI3_ SPI3 _E_D AT TABLE 132 – SPI-3 AC INPUT / OUTPUT TIMING SPECIFICATIONS ...
Page 81
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 11.6.2 SPI-4 LVDS Input / Output SPI-4 input and output timing is shown in the following paragraph. Double Data Rate protocol is used for data and status transfer. The SPI-4 LVDS signals use a dynamic data alignment at the ingress. S PI4 ...
Page 82
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 TABLE 133 – SPI-4.2 LVDS AC INPUT / OUTPUT TIMING SPECIFICATIONS Inputs Unit Min. Typ. Duty cycle % 45 50 Frequency (DDR) MHz 80 — Frequency (DDR) MHz 200 311 TR 300 — Deskew UI — — Outputs Duty cycle % 45 50 Frequency (DDR) ...
Page 83
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 11.6.6.1 Microprocessor parallel port AC timing specifications Be sure to connect SPI_EN to a logic low when using the parallel µP interface mode. Read cycle specification Motorola non-multiplexed (MPM=0) DSB + CSB R/WB ADD[5:0] READ DBUS[7:0] Figure 36. Microprocessor parallel port Motorola read timing diagram TABLE 138 – ...
Page 84
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Write cycle specification Motorola non-multiplexed (MPM=0) DSB + CSB R/WB ADD[5:0] Write DBUS[7:0] Figure 37. Microprocessor parallel port Motorola write timing diagram TABLE 139 – MICROPROCESSOR PARALLEL PORT MOTOROLA WRITE TIMING Symbol Parameter T Internal main clock period (MCLK) t Write cycle time ...
Page 85
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Read cycle specification Intel non-multiplexed bus (MPM=1) CSB + RDB ADD[5:0] Read DBUS[7:0] : NOTE 1. WRB should be tied to High. Figure 38. Microprocessor parallel port Intel mode read timing diagram TABLE 140 – MICROPROCESSOR PARALLEL PORT INTEL MODE READ TIMING ...
Page 86
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Write cycle specification Intel non-multiplexed bus (MPM=1) WRB + CSB ADD[5:0] Write DBUS[7:0] : NOTE 1. RDB should be tied to a logic one. Figure 39. Microprocessor parallel port Intel mode write timing diagram TABLE 141 – MICROPROCESSOR PARALLEL PORT INTEL MODE WRITE TIMING ...
Page 87
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 11.6.6.2 Serial microprocessor interface (serial peripheral interface mode) Timing Characteristics The maximum SPI Data transfer clock frequency is 2 MHz. The detail information of the timing characteristics is shown in below and timing diagram is shown in Figure 40, Microprocessor serial peripheral interface timing diagram. ...
Page 88
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 12. MECHANICAL CHARACTERISTICS 12.1 Device overview ...
Page 89
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 12.2 Pin name/ball location table SIGNAL PIN NAME BALL SIGNAL PIN NAME RESERVED A4 RESERVED RESERVED E5 RESERVED RESERVED B4 RESERVED RESERVED D4 RESERVED RESERVED A3 RESERVED RESERVED C4 RESERVED RESERVED B3 RESERVED RESERVED C2 RESERVED RESERVED C1 RESERVED RESERVED C3 RESERVED RESERVED D3 RESERVED RESERVED D1 RESERVED RESERVED ...
Page 90
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 12.2. Pin name/ball location table (continued) SIGNAL PIN NAME BALL SIGNAL PIN NAME RESERVED RESERVED AK17 RESERVED RESERVED AN16 RESERVED RESERVED AP16 RESERVED RESERVED AL17 RESERVED RESERVED AK18 RESERVED AM17 RESERVED RESERVED RESERVED AN17 RESERVED RESERVED AP17 ...
Page 91
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 12.2 Pin name/ball location table (continued) SIGNAL PIN NAME BALL SIGNAL PIN NAME SPI3A_E_DAT[2] SPI3A_E_DAT[29] A26 SPI3A_E_DAT[28] E25 SPI3A_E_DAT[1] SPI3A_E_DAT[27] D25 SPI3A_E_DAT[0] SPI3A_E_FCLK SPI3A_E_DAT[26] C25 SPI3A_PTPA SPI3A_E_DAT[25] A25 SPI3A_TADR[7] SPI3A_E_DAT[24] B25 SPI3A_TADR[6] SPI3A_E_DAT[23] C24 SPI3A_TADR[5] SPI3A_E_DAT[22] D24 ...
Page 92
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 12.3 Device package The SPI Exchange IDT88P8341 device is packaged 820-ball one millimeter ball pitch thermally-enhanced plastic ball grid array. All balls, whether used or unused, must be soldered to pads. Figure 41. IDT88P8341 820PBGA package, bottom view 92 INDUSTRIAL TEMPERATURE RANGE ...
Page 93
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 Figure 42. IDT88P8341 820PBGA package, top and side views INDUSTRIAL TEMPERATURE RANGE 93 APRIL 10, 2006 ...
Page 94
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 13. GLOSSARY ACRONYM FIFO First In First Out memory LID Logical IDentifier See also Logical Port (LP) The entity associated with a flow of data between a SPI SPI-4 LP SPI SPI-3 LP. LP Logical Port. See also Logical Identifier (LID) The entity associated with a SPI-3 or SPI-4 address ...
Page 95
... IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4 14. DATASHEET DOCUMENT REVISION HISTORY ISSUE DATE • 0.7 05/21/04 General Release • 0.8 10/01/04 AG30 ball location changed to SPI4_I_STAT_N[1] and AF31 ball location changed to SPI4_I_STAT_P[0] on Pin name/ball location table (Table 12.2) on page 88. • 0.9 03/01/05 Updated Chip Configuration Sequence (p. 40) • Update Table 21: “BIT Order Within a 16-BIT Address Register” (p. 44) • ...
Page 96
ORDERING INFORMATION IDT X X Device Type Package NOTE: 1. Green parts are available. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 X X Process / Temperature Range 88P8341 for SALES: 800-345-7015 or ...