IDT88P8341 Integrated Device Technology, IDT88P8341 Datasheet - Page 70

• Manufacturer Part Number: IDT88P8341
• Description: Spi Exchange Spi-3 To Spi-4
• Manufacturer: Integrated Device Technology

ous training on the SPI-4 ingress status interface.
2 errors on the SPI-4 ingress status interface programmed into the I_DIP_NUM
field. After the DIP-2 errors are inserted, the I_ERR_INS field will clear itself.
programmed into the I_DIP_NUM field on the SPI-4 egress status interface..
SPI-4 ingress DIP-4 error counter (Block_base
0x0300 + Register_offset 0x10)
TABLE 98 - SPI-4 INGRESS DIP-4 ERROR
COUNTER (REGISTER_OFFSET 0x10)
0x0300 + Register_offset 0x10. The SPI-4 ingress DIP-4 error counter has
read access, and automatically clears itself after a read. The SPI-4 ingress DIP-
4 error counter is used in port diagnostics to verify the integrity of the SPI-4
ingress data path.
the SPI-4 egress status interface. The DIP_4 field saturates at the value
0xFFFF, and is automatically cleared after reading to re-start DIP-4 error
counter accumulation.
SPI-4 ingress bit alignment control register
(Block_base 0x0300 + Register_offset 0x11)
TABLE 99 - SPI-4 INGRESS BIT ALIGNMENT
CONTROL REGISTER (REGISTER_OFFSET 0x11)
0x0300 + Register_offset 0x11. The SPI-4 ingress bit alignment control register
has read and write access. The SPI-4 ingress bit alignment control register is
used to overrule the automatically selected bit phase alignments and go to
manual mode. In manual mode, the PHASE_ASSIGN field [Block_base 0x0800
+ Register_offset 0x0c – 0x1F] now defines the selected phase.
SPI-4 ingress start up training threshold register
(Block_base 0x0300 + Register_offset 0x12)
TABLE 100 - SPI-4 INGRESS START UP TRAINING
THRESHOLD REGISTER (REGISTER_OFFSET 0x12)
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
I_FORCE_TRAIN
I_ERR_INS
I_DIP_NUM
The I_DIP_NUM field is used to create the number of DIP-2 errors
The SPI-4 ingress DIP-4 error counter is addressed from Block_base
DIP_4 The DIP_4 field is used to read the number of DIP-4 errors seen on
The SPI-4 ingress bit alignment control register is addressed from Block_base
FORCE The FORCE field is used to manually align the SPI-4 ingress data.
DIP_4
FORCE
STRT_TRAIN
Field
Field
Field
0=Normal status channel operation
1=Force continuous training on the SPI-4 ingress status interface
0=Normal status channel operation
1= Insert DIP-2 errors on the SPI-4 ingress status interface
0=Normal bit alignment operation
the PHASE_ASSIGN field.
1= Force to manual bit alignment mode on SPI-4 ingress data using
The I_ERR_INS field is used to insert the number of DIP-
The I_FORCE_TRAIN field is used to force continu-
Bits
15:0
Bits
Bits
7:0
0
Length
Length
Length
16
1
8
Initial Value
Initial Value
Initial Value
0
0
0
70
Block_base 0x0300 + Register_offset 0x12. The SPI-4 ingress start up training
threshold register has read and write access. The SPI-4 ingress start up training
threshold register is used to set the number of consecutive training patterns that
will lead to OUT_OF_SYNCH on the SPI-4 ingress data. If the STRT_TRAIN
field is set to zero, then the OUT_OF_SYNCH feature is disabled.
consecutive training patterns that will lead to OUT_OF_SYNCH on the SPI-4
ingress data interface.
9.4.5 Common module block base 0x0400 registers
SPI-4 egress LID to LP map (Block_base 0x0400 +
Register_offset 0x00 - 0x3F)
TABLE 101 - SPI-4 EGRESS LID TO LP MAP
(256 ENTRIES)
interface. The entries are at Block_base 0x0400 + LID. For example, LID 0x00
is at Block_base 0x0400 + 0x00. A SPI-4 egress LID to LP map has read and
write access. A SPI-4 egress LID to LP map is used to map a logical identifier
used internally to a SPI-4 egress logical port.
LID0. Therefore all the LPs that have entries in the calendar tables should be
enabled.
the register address. Eight bits support the 256 possible LPs on the SPI-4
physical interface. Only 64 LPs are supported in the IDT88P8341 device.
9.4.6 Common module block base 0x0500 registers
SPI-4 egress calendar_0 (Block_base 0x0500 +
Register_offset 0x00 – 0xFF)
TABLE 102 - SPI-4 EGRESS CALENDAR_0
(256 LOCATIONS)
write access. When the SPI-4 egress calendar_0 is selected, calendar_0 is
in use. There are 256 entries in the SPI-4 egress calendar_0 to schedule the
updating of the FIFO status channel LPs to the attached device. If less than the
maximum 256 LPs are needed on the SPI-4 interface, the calendar entries
should be used for scheduling more frequent status updated for higher-speed
LPs. The value of time-critical LPs must appear multiple times in the table. For
example, a multi-PHY SPI-4 could have OC-48 channels appear in the
calendar at four times the rate of OC-12 channels, since the higher data rate
of the OC-48 channels would benefit from more frequent FIFO status channel
updates. The LP field values range from 0x00 to 0xFF. The IDT88P8341 and
the attached devices must have identical calendars.
The SPI-4 ingress start up training threshold register is addressed from
STRT_TRAIN
There are 64 entries in the SPI-4 egress LID to LP map for the SPI-4 ingress
Data for an inactive LP having an entry in the calendar is forwarded to
LP The LP programmed is associated to the LID with the same number as
EN The EN bit is used to enable or disable the connection of a LID to an LP.
The SPI-4 egress calendar_0 is at Block_base 0x0500 and has read and
LP
EN
LP
Field
Field
0=LP is disabled
1=LP is enabled
The STRT_TRAIN field is used to set the number of
Bits
Bits
7:0
7:0
INDUSTRIAL TEMPERATURE RANGE
8
Length
Length
8
1
8
APRIL 10, 2006
Initial Value
Initial Value
0x00
0b0
0xFF