MT58L1MY18D Micron Semiconductor Products, Inc., MT58L1MY18D Datasheet - Page 24

• Manufacturer Part Number: MT58L1MY18D
• Description: 18Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O; 2.5V Vdd, 2.5V I/O, Pipelined, Dcd,
• Manufacturer: Micron Semiconductor Products, Inc.

Performing a TAP Reset
five rising edges of TCK. This RESET does not affect the
operation of the SRAM and may be performed while
the SRAM is operating.
that TDO comes up in a High-Z state.
TAP Registers
balls and allow data to be scanned into and out of the
SRAM test circuitry. Only one register can be selected
at a time through the instruction register. Data is seri-
ally loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of
TCK.
Instruction Register
the instruction register. This register is loaded when it
is placed between the TDI and TDO balls as shown in
Figure 16. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state as described in the previous section.
the two least significant bits are loaded with a binary
“01” pattern to allow for fault isolation of the board-
level serial test data path.
Bypass Register
isters, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the SRAM with mini-
mal delay. The bypass register is set LOW (Vss) when
the BYPASS instruction is executed.
Boundary Scan Register
input and bidirectional balls on the SRAM. The SRAM
has a 75-bit-long register.
tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
Shift-DR state. The EXTEST, SAMPLE/PRELOAD and
SAMPLE Z instructions can be used to capture the
contents of the I/O ring.
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03
A reset is performed by forcing TMS HIGH (V
At power-up, the TAP is reset internally to ensure
Registers are connected between the TDI and TDO
Three-bit instructions can be serially loaded into
When the TAP controller is in the Capture-IR state,
To save time when serially shifting data through reg-
The boundary scan register is connected to all the
The boundary scan register is loaded with the con-
DD
) for
24
PIPELINED, DCD SYNCBURST SRAM
which the bits are connected. Each bit corresponds to
one of the bumps on the SRAM package. The MSB of
the register is connected to TDI, and the LSB is con-
nected to TDO.
Identification (ID) Register
bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction regis-
ter. The IDCODE is hardwired into the SRAM and can
be shifted out when the TAP controller is in the Shift-
DR state. The ID register has a vendor code and other
information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
three-bit instruction register. All combinations are
listed in the Instruction Codes table. Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.
compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EXTEST or INTEST
or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
ing the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state,
instructions are shifted through the instruction regis-
ter through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller
needs to be moved into the Update-IR state.
EXTEST
to be executed whenever the instruction register is
loaded with all 0s. EXTEST is not implemented in this
SRAM TAP controller, and therefore this device is not
compliant to 1149.1.
tion. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a SAM-
PLE/PRELOAD instruction has been loaded. There is
18Mb: 1 MEG x 18, 512K x 32/36
The Boundary Scan Order tables show the order in
The ID register is loaded with a vendor-specific, 32-
Eight different instructions are possible with the
The TAP controller used in this SRAM is not fully
Instructions are loaded into the TAP controller dur-
EXTEST is a mandatory 1149.1 instruction which is
The TAP controller does recognize an all-0 instruc-
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©2003 Micron Technology, Inc.