MT58L128L32F1 Micron Semiconductor Products, Inc., MT58L128L32F1 Datasheet - Page 8

• Manufacturer Part Number: MT58L128L32F1
• Description: 4Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

FBGA PIN DESCRIPTIONS
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_F.p65 – Rev. F, Pub. 1/03 EN
8P, 8R, 9P, 9R,
10A, 10B, 10P, 9R, 10A, 10B,
10R, 11A, 11R 10P, 10R, 11R
2A, 2B, 3P,
3R, 4P, 4R,
x18
11H
4A
7A
3A
6A
9A
6R
6P
5B
7B
6B
3B
8B
–
–
2A, 2B, 3P,
3R, 4P, 4R,
8P, 8R, 9P,
x32/x36
11H
5A
4A
7A
3A
6A
9A
6R
6P
5B
4B
7B
6B
3B
8B
SYMBOL
OE#(G#)
BWb#
BWd#
BWa#
BWE#
ADV#
BWc#
GW#
CE2#
SA0
SA1
CLK
CE#
CE2
SA
ZZ
TYPE
Input Synchronous Address Inputs: These inputs are registered and must
Input
Input
Input
Input
Input
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Snooze Enable: This active HIGH, asynchronous input causes the
Input Synchronous Chip Enable: This active HIGH input is used to enable
Input
Input Synchronous Address Advance: This active LOW input is used to
(continued on next page)
meet the setup and hold times around the rising edge of CLK.
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For
the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#
controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
controls DQds and DQPd. Parity is only available on the x18 and x36
versions.
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
the device and is sampled only when a new external address is
loaded.
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
the device and is sampled only when a new external address is
loaded.
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on ADV# effectively causes wait
states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
FLOW-THROUGH SYNCBURST SRAM
8
4Mb: 256K x 18, 128K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2003, Micron Technology, Inc.