MT58L128L32F1 Micron Semiconductor Products, Inc., MT58L128L32F1 Datasheet - Page 12

• Manufacturer Part Number: MT58L128L32F1
• Description: 4Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

TRUTH TABLE
NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_F.p65 – Rev. F, Pub. 1/03 EN
OPERATION
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or
3. BWa# enables WRITEs to DQas and DQPa. BWb# enables WRITEs to DQbs and DQPb. BWc# enables WRITEs to DQcs and
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
DQPc. BWd# enables WRITEs to DQds and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc
and DQPd are only available on the x36 version.
throughout the input data hold time.
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
ADDRESS
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
None
None
None
None
None
USED
Next
Next
Next
Next
Next
Next
CE# CE2# CE2
H
X
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
H
H
X
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
FLOW-THROUGH SYNCBURST SRAM
12
ZZ ADSP# ADSC# ADV# WRITE# OE#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
4Mb: 256K x 18, 128K x 32/36
X
H
H
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
H
H
H
X
X
X
X
X
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
©2003, Micron Technology, Inc.
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
D
Q
Q
Q
D
D
Q
Q
D
D