MT58L128L32F1 Micron Semiconductor Products, Inc., MT58L128L32F1 Datasheet - Page 22

• Manufacturer Part Number: MT58L128L32F1
• Description: 4Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

WRITE TIMING PARAMETERS
NOTE: 1. D(A2) refers to output from address A2. D(A2 + 1) refers to output from the next internal burst address following A2.
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_F.p65 – Rev. F, Pub. 1/03 EN
SYMBOL
t
f
t
t
t
t
t
t
t
KC
KF
KH
KL
OEHZ
AS
ADSS
AAS
WS
BWa#-BWd#
ADDRESS
(NOTE 2)
ADSC#
ADSP#
BWE#,
ADV#
GW#
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or GW#
OE#
CLK
CE#
D
Q
is HIGH, CE2# is HIGH and CE2 is LOW.
data contention for the time period prior to the byte write enable inputs being sampled.
HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
7.5
2.5
2.5
1.5
1.5
1.5
1.5
-6.8
BURST READ
133
3.5
High-Z
t ADSS
8.8
2.5
2.5
1.5
1.5
1.5
1.5
t CES
t AS
-7.5
A1
t ADSH
t CEH
t AH
t KH
t OEHZ
113
(NOTE 3)
4.2
BYTE WRITE signals are
ignored when ADSP# is LOW.
t KC
t ADSS
t KL
Single WRITE
t DS
D(A1)
3.0
3.0
1.8
1.8
1.8
1.8
10
-8.5
t ADSH
t DH
100
5.0
A2
4.0
4.0
2.0
2.0
2.0
2.0
15
-10
(NOTE 4)
5.0
66
D(A2)
(NOTE 5)
WRITE TIMING
MHz
ns
ns
ns
ns
ns
ns
ns
ns
D(A2 + 1)
(NOTE 1)
t WS
BURST WRITE
FLOW-THROUGH SYNCBURST SRAM
22
t WH
SYMBOL
t
t
t
t
t
t
t
t
DS
CES
AH
ADSH
AAH
WH
DH
CEH
D(A2 + 1)
4Mb: 256K x 18, 128K x 32/36
ADV# suspends burst.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D(A2 + 2)
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1.5
-6.8
ADSC# extends burst.
D(A2 + 3)
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1.5
-7.5
t ADSS
A3
D(A3)
t ADSH
1.8
0.5
0.5
0.5
0.5
0.5
0.5
1.8
-8.5
Extended BURST WRITE
t WS
t AAS
D(A3 + 1)
t AAH
t WH
©2003, Micron Technology, Inc.
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2.0
-10
DON’T CARE
D(A3 + 2)
ns
ns
ns
ns
ns
ns
ns
ns