MT58L128L32F1 Micron Semiconductor Products, Inc., MT58L128L32F1 Datasheet

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MT58L128L32F1

Manufacturer Part Number
MT58L128L32F1
Description
4Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
Manufacturer
Micron Semiconductor Products, Inc.
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT58L128L32F1-10ITA
Manufacturer:
MAXIM
Quantity:
4 162
4Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
• Separate +3.3V or +2.5V isolated output buffer
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down
• 165-pin FBGA package
• 100-pin TQFP package
• Low capacitive bus loading
• x18, x32, and x36 versions available
OPTIONS
• Timing (Access/Cycle/MHz)
• Configurations
• Packages
• Operating Temperature Range
* A Part Marking Guide for the FBGA devices can be found on Micron’s
** Industrial temperature range offered in specific speed grades and
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_F.p65 – Rev. F, Pub. 1/03 EN
Web site—http://www.micron.com/support/index.html.
configurations. Contact factory for more information.
supply (V
and address pipelining
I/Os and control signals
6.8ns/7.5ns/133 MHz
7.5ns/8.8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
3.3V I/O
2.5V I/O
100-pin TQFP
165-pin FBGA
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
256K x 18
128K x 32
128K x 36
256K x 18
128K x 32
128K x 36
DD
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
Q)
MT58L256L18F1T-8.5
Part Number Example:
MT58L256V18F1
MT58L128V32F1
MT58L128V36F1
MT58L256L18F1
MT58L128L32F1
MT58L128L36F1
MARKING
None
-6.8
-7.5
-8.5
-10
F*
IT
T
DD
)
FLOW-THROUGH SYNCBURST SRAM
1
MT58L256L18F1, MT58L128L32F1,
MT58L128L36F1; MT58L256V18F1,
MT58L128V32F1, MT58L128V36F1
3.3V V
GENERAL DESCRIPTION
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
18, 128K x 32, or 128K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock in-
put (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2#, CE2), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#) and global write
(GW#).
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
The Micron
Micron’s 4Mb SyncBurst SRAMs integrate a 256K x
4Mb: 256K x 18, 128K x 32/36
DD
, 3.3V or 2.5V I/O, Flow-Through
®
SyncBurst
100-Pin TQFP
165-Pin FBGA
SRAM family employs
1
©2003, Micron Technology, Inc.

Related parts for MT58L128L32F1

MT58L128L32F1 Summary of contents

Page 1

... Contact factory for more information. 4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM MT58L256L18F1_F.p65 – Rev. F, Pub. 1/03 EN PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH SYNCBURST SRAM ™ MT58L256L18F1, MT58L128L32F1, MT58L128L36F1; MT58L256V18F1, MT58L128V32F1, MT58L128V36F1 3. MARKING -6 ...

Page 2

ADDRESS SA0, SA1, SA REGISTER MODE ADV# CLK ADSC# ADSP# BYTE “b” WRITE REGISTER BWb# BYTE “a” WRITE REGISTER BWa# BWE# GW# ENABLE CE# REGISTER CE2 CE2# OE# 17 SA0, SA1, SA MODE ADV# CLK ADSC# ADSP# BYTE “d” ...

Page 3

GENERAL DESCRIPTION (continued) Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also ...

Page 4

ADV# 83 ADSP# 84 ADSC# 85 ...

Page 5

TQFP PIN DESCRIPTIONS x18 x32/x36 SYMBOL 32–35, 44–50, 32–35, 44–50, 80–82, 99, 81, 82, 99, 100 100 93 93 BWa BWb# – 95 BWc# – 96 BWd BWE GW# 89 ...

Page 6

TQFP PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 85 85 ADSC MODE 64 64 (a) 58, 59, (a) 52, 53, DQa 62, 63, 68, 69, 56–59, 62, 63 72 12, (b) 68, 69 ...

Page 7

CE# BWb# NC CE2# BWE CE2 NC BWa# CLK GW ...

Page 8

FBGA PIN DESCRIPTIONS x18 x32/x36 SYMBOL 2A, 2B, 3P, 2A, 2B, 3P, 3R, 4P, 4R, 3R, 4P, 4R, 8P, 8R, 9P, 9R, 8P, 8R, 9P, 10A, 10B, 10P, 9R, 10A, 10B, 10R, 11A, 11R 10P, 10R, ...

Page 9

FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 9B 9B ADSP ADSC MODE (LB0#) (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, 11M (b) 1J, 1K, (b) 10D, ...

Page 10

FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 1H, 2H, 4C, 4N, 1H, 2H, 4C, 4N, 5C, 5D, 5E 5F, 5C, 5D, 5E 5F, 5G, 5H, 5J, 5K, 5G, 5H, 5J, 5K, 5L, 5M, 6C, 6D, 5L, 5M, 6C, 6D, 6E, ...

Page 11

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS ...

Page 12

TRUTH TABLE OPERATION ADDRESS DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, ...

Page 13

ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply DD Relative to V .................................... -0.5V to +4.6V SS Voltage Supply DD Relative to V .................................... -0.5V to +4. -0. 0. Storage ...

Page 14

TQFP CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance FBGA CAPACITANCE DESCRIPTION Address/Control Input Capacitance Output Capacitance (Q) Clock Capacitance NOTE: 1. This parameter is sampled. 2. Preliminary package data. 4Mb: 256K x 18, 128K x ...

Page 15

I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0°C ≤ T ≤ +70° +3.3V +0.3V/-0.165V DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage ...

Page 16

TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) Thermal Resistance (Junction to Top of Case) FBGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient Test conditions follow standard test methods (Airflow of 1m/s) Junction to ...

Page 17

I OPERATING CONDITIONS AND MAXIMUM LIMITS DD (Note 1) (0°C ≤ T ≤ +70° DESCRIPTION CONDITIONS Device selected; All inputs ≤ V Power Supply or ≥ Cycle time ≥ Current: IH Operating V = MAX; ...

Page 18

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (0°C ≤ T ≤ +70° DESCRIPTION SYMBOL Clock t Clock cycle time KC f Clock frequency KF t Clock HIGH time KH t Clock LOW time KL Output ...

Page 19

I/O AC TEST CONDITIONS Input pulse levels ................. V .................... V Input rise and fall times ..................................... 1ns Input timing reference levels ..................... V Output reference levels ............................ V Output load ............................. See Figures 1 and 2 3.3V I/O ...

Page 20

SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced The duration of SNOOZE MODE dictated by the length of time ...

Page 21

KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, GW#, BWa#-BWd# t CES t CEH CE# (NOTE 2) ADV# OE# t OEQ t KQLZ Q(A1) ...

Page 22

KC CLK ADSS t ADSH ADSP# t ADSS ADSC ADDRESS A1 BYTE WRITE signals are ignored when ADSP# is LOW. BWE#, BWa#-BWd# GW# t CES t CEH CE# (NOTE 2) ...

Page 23

KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, BWa#-BWd# t CES t CEH (NOTE 4) CE# (NOTE 2) ADV# OE# D High-Z Q Q(A1) Q(A2) Back-to-Back READs ...

Page 24

TYP +0.06 0.32 -0.10 PIN #1 ID NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per ...

Page 25

BALL A11 165X Ø 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40 7.50 ±0.05 15.00 ±0.10 7.00 ±0.05 NOTE: 1. All dimensions in millimeters MAX or typical where noted. DATA SHEET ...

Page 26

REVISION HISTORY Updated package drawings ................................................................................................................................... January 9/03 Removed "Preliminary Package Data" from front page .............................................................................. February 22/02 Removed 119-pin PBGA package and references ........................................................................................ February 14/02 Removed note "Not Recommended for New Designs," Rev. 6/01 ...................................................................... June 7/01 Added ...

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