MT58L128L32F1 Micron Semiconductor Products, Inc., MT58L128L32F1 Datasheet - Page 6

• Manufacturer Part Number: MT58L128L32F1
• Description: 4Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

TQFP PIN DESCRIPTIONS (continued)
4Mb: 256K x 18, 128K x 32/36 Flow-Through SyncBurst SRAM
MT58L256L18F1_F.p65 – Rev. F, Pub. 1/03 EN
62, 63, 68, 69, 56–59, 62, 63
21, 26, 40, 55, 21, 26, 40, 55,
78, 79, 95, 96
15, 41, 65, 91 15, 41, 65, 91
54, 61, 70, 77 54, 61, 70, 77
1–3, 6, 7, 16,
4, 11, 20, 27,
5, 10, 14, 17,
(b)
13, 18, 19,
25, 28–30,
51–53, 56,
57, 66, 75,
(a)
60, 67, 71,
72, 73
22, 23
42, 43
76, 90
38, 39
8, 9, 12,
x18
58, 59,
85
31
64
74
24
–
–
72–75, 78, 79
22–25, 28, 29
4, 11, 20, 27,
5, 10, 14, 17,
(c)
(b)
(d)
(a)
60, 67, 71,
x32/x36
12, 13
16, 66
42, 43
76, 90
38, 39
2, 3, 6–9,
52, 53,
68, 69,
18, 19,
85
31
64
51
80
30
1
NC/DQPb
NC/DQPd
NC/DQPa
NC/DQPc
SYMBOL
ADSC#
MODE
V
DQa
D Q b
D Q d
DQc
DNU
V
V
N C
N F
ZZ
DD
DD
SS
Q
Output “b” is DQb pins. For the x32 and x36 versions, Byte “a” is DQa
Supply Power Supply: See DC Electrical Characteristics and Operating
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Supply Ground: GND.
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte
TYPE
Input
Input
Input
NC/
I/O
–
–
–
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
Mode: This input selects the burst sequence. A LOW on this pin
selects “linear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is
DQd pins. Input data must meet setup and hold times around
the rising edge of CLK.
No Connect/Parity Data I/Os: On the x32 version, these pins are
No Connect (NC). On the x18 version, Byte “a” parity is DQPa;
Byte “b” parity is DQPb. On the x36 version, Byte “a” parity is
DQPa; Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte
“d” parity is DQPd.
Conditions for range.
Operating Conditions for range.
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
No Connect: These signals are not internally connected and
may be connected to ground to improve package heat
dissipation.
No Function: These pins are internally connected to the die and
will have the capacitance of input pins. It is allowable to leave
these pins unconnected or driven by signals. Reserved for
address expansion, pin 43 becomes an SA at 8Mb density and
pin 42 becomes an SA at 16Mb density.
FLOW-THROUGH SYNCBURST SRAM
6
4Mb: 256K x 18, 128K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2003, Micron Technology, Inc.