MT55L1MY18F Micron Semiconductor Products, Inc., MT55L1MY18F Datasheet - Page 23

• Manufacturer Part Number: MT55L1MY18F
• Description: 18Mb ZBT SRAM, 3.3V Vdd, 2.5V or 3.3V I/O; 2.5V Vdd, 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

IEEE 1149.1 Serial Boundary Scan
(JTAG)
access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the
set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are
excluded because their inclusion places an added
delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not
conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
JTAG function is not to be implemented. Upon pow-
erup, the device will come up in a reset state which will
not interfere with the operation of the device.
NOTE:
18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM
MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03
1
0
The SRAM incorporates a serial boundary scan test
The SRAM contains a TAP controller, instruction
These balls can be left floating (unconnected), if the
The 0/1 next to each state represents the value
of TMS at the rising edge of TCK.
TEST-LOGIC
RUN-TEST/
RESET
IDLE
0
TAP Controller State Diagram
1
Figure 15:
1
0
CAPTURE-DR
UPDATE-DR
PAUSE-DR
DR-SCAN
SHIFT-DR
EXIT1-DR
EXIT2-DR
1
SELECT
0
0
1
0
1
1
0
1
1
0
0
1
0
CAPTURE-IR
UPDATE-IR
PAUSE-IR
1
EXIT1-IR
EXIT2-IR
IR-SCAN
SHIFT-IR
SELECT
0
0
1
0
1
1
0
1
1
0
0
23
Test Access Port (Tap)
Test Clock (TCK)
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
Test MODE SELECT (TMS)
controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.
Test Data-In (TDI)
into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 15. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most signifi-
cant bit (MSB) of any register. (See Figure 16.)
Test Data-Out (TDO)
out from the registers. The output is active depending
upon the current state of the TAP state machine. (See
Figure 15.) The output changes on the falling edge of
TCK. TDO is connected to the least significant bit
(LSB) of any register. (See Figure 16.)
NOTE:
18Mb: 1 MEG x 18, 512K x 32/36
TMS
TCK
TDI
The test clock is used only with the TAP controller.
The TMS input is used to give commands to the TAP
The TDI ball is used to serially input information
The TDO output ball is used to serially clock data-
X = 74 for all configurations.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TAP Controller Block Diagram
Selection
Circuitry
FLOW-THROUGH ZBT SRAM
TAP CONTROLLER
Boundary Scan Register*
Figure 16:
31
Identification Register
x
30
Instruction Register
.
29
.
Bypass Register
.
.
.
.
.
.
2
2
2
1
1
1
0
0
0
0
©2003 Micron Technology, Inc.
Selection
Circuitry
TDO