MT55L1MY18F Micron Semiconductor Products, Inc., MT55L1MY18F Datasheet
MT55L1MY18F
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MT55L1MY18F Summary of contents
Page 1
... Contact Factory for availability of Industrual Temperature devices. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM MT55L1MY18F, MT55V1MV18F, ...
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... ZBT SRAM uses a LATE WRITE cycle. For example WRITE cycle begins in clock 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM cycle one, the address is present on rising edge one. ...
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... NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin/ball descriptions, and tim- ing diagrams for detailed information. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 Figure 3: Functional Block Diagram 1 Meg x 18 ...
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... Pin 16 does not have to be connected directly Pins 43 and 42 are reserved for address expansion; 36Mb and 72Mb, respectively. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 Figure 5: Pin Layout (Top View) 100-Pin TQFP ...
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... Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for DD range. V Supply Ground: GND. SS 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 ©2003 Micron Technology, Inc. ...
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... No Function: These pins are internally connected to the die and have the capacitance of an input pin. They may be left floating, driven by signals, or connected to ground to improve package heat dissipation. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM DESCRIPTION Micron Technology, Inc ...
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... No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2. Balls 2R and 2P are reserved for address expansion; 36Mb and 72Mb, respectively. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 Figure 6: Ball Layout (Top View) ...
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... NF/DQPc is DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd. NF/DQPd 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... No Function: These balls are internally connected to the die and have the capacitance of an input pin. They may be left floating, driven by signals, or connected to ground to improve package heat dissipation. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM DESCRIPTION Micron Technology, Inc ...
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... L WRITE All Byte L L WRITE ABORT/NOP NOTE: Using R/W# and byte write(s), any one or more bytes may be written. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 SECOND ADDRESS THIRD ADDRESS (INTERNAL) X…X01 X…X00 X…X11 X…X10 ...
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... A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the clock (CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock (CLK). 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 Figure 7: State Diagram For ZBT SRAM ...
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... The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE. 11. The address counter is incremented for all CONTINUE BURST CYCLES. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 ADV/ CE# ...
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... Output Low Voltage Supply Voltage Isolated Output Buffer Supply 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, ...
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... Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 £ +70º CONDITIONS SYMBOL Data bus (DQx) ...
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... Note 10; notes appear following parameter tables on page 18 DESCRIPTION Junction to Ambient (Airflow if 1m/s, two-layer board) and procedures for measuring thermal impedance, per Junction to Case (Top) Junction to Board (Bottom) 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 CONDITIONS T = 25° MHz 3.3V DD ...
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... All inputs £ V All inputs static; CLK frequency = 0 Device deselected; V Clock Running ADV/LD# ³ 0.2; Cycle time ³ Snooze Mode 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 Operating Conditions and Maximum Limits £ +70º CONDITIONS IL t ...
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... OE# to output in High-Z Setup Times Address Clock enable (CKE#) Control signals Data-in Hold Times Address Clock enable (CKE#) Control signals Data-in 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 -8.8 -10 SYMBOL MIN MAX MIN t 8.8 10.0 KHKH ...
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... Typical values are measured at 3.3V, 25 12ns cycle time. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 (GND). 9. Typical values are measured at 2.5V, 25 12ns cycle time. ...
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... Data coherency is provided for all possible operations READ is initiated, the most current data is used. The most recent data may be from the input data register. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 Figure 8: ...
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... Data coherency is provided for all possible operations READ is initiated, the most current data is used. The most recent data may be from the input data register. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 Figure 9: ...
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... ISB2Z ALL INPUTS (except ZZ) Outputs (Q) 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM The asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ becomes a logic HIGH, I ...
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... Figure 12: +3.3V Q 351 NOTE: For Figures 11 and 13, 30pF = distributive test jig capacitance. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 2. /2.2) + 1.5V Input pulse levels.......................... /2. Input rise and fall times ............................................. 1ns /2 ...
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... NOTE: The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 Test Access Port (Tap) Test Clock (TCK) The test clock is used only with the TAP controller. ...
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... The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM one of the balls on the SRAM package. The MSB of the ...
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... Because there is a large difference in the clock frequencies possible that during the Capture-DR state, an input or output will undergo a 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM transition. The TAP may then try to capture a signal while in transition (metastable state) ...
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... CH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the loads in Figures 18 and 19. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM ...
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... SS 2. TAP control balls only. For boundary scan ball specifications, please refer to the I/O DC Electrical Characteristics and Operation Conditions tables. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 2.5V TAP AC Test Conditions Input Pulse Levels........................................... Vss to 2.5V Input rise and fall times ...
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... SAMPLE/PRELOAD RESERVED 101 RESERVED 110 BYPASS 111 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 DESCRIPTION 0000 Reserved for version number. 00111 Defines depth of 1Mb. 00110 Defines depth of 512K. 00011 Defines width of x18 bits. ...
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... ADV/LD# 36 OE# (G#) 37 CKE# 38 R/W# 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM BALL ID BIT 11P 10R 46 10P 47 11R ...
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... DQb ADV/LD# 36 OE# (G#) 37 CKE# 38 R/W# 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM BALL ID BIT 11P 10R 46 10P 47 11R ...
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... DQb 29 DQPb ADV/LD# 36 OE# (G#) 37 CKE# 38 R/W# 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM BALL ID BIT 11P 10R 46 10P 47 11R ...
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... NOTE: 1. All dimensions in inches (millimeters) 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 Figure 20: 100-Pin Plastic TQFP (JEDEC LQFP) 0.625 14.00 ± ...
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... Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc., 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 Figure 21: 165-Ball FBGA 0 ...
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... Corrected grammatical errors • New ADVANCE data sheet for 0.16µm process; Rev A; Pub. 6/02 ...........................................................................6/02 18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03 18Mb: 1 MEG x 18, 512K x 32/36 FLOW-THROUGH ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. ...