MT55L1MY18F Micron Semiconductor Products, Inc., MT55L1MY18F Datasheet - Page 2

• Manufacturer Part Number: MT55L1MY18F
• Description: 18Mb ZBT SRAM, 3.3V Vdd, 2.5V or 3.3V I/O; 2.5V Vdd, 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

for easy depth expansion (CE2, CE2#), cycle start input
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc#, and BWd#), and
read/write (R/W#).
(OE#, which may be tied LOW for control signal mini-
mization), clock (CLK) and snooze enable (ZZ, which
may be tied LOW if unused). There is also a burst mode
pin/ball (MODE) that selects between interleaved and
linear burst modes. MODE may be tied HIGH, LOW or
left unconnected if burst is unused. The data out (Q) is
enabled by OE#. WRITE cycles can be from one to four
bytes wide as controlled by the write control inputs.
ated by the ADV/LD# input. Subsequent burst
addresses can be internally generated as controlled by
the burst advance pin/ball (ADV/LD#). Use of burst
mode is optional. It is allowable to give an address for
each individual READ and WRITE cycle. BURST cycles
wrap around after the fourth access from a base
address.
bus, the flow-through ZBT SRAM uses a LATE WRITE
cycle. For example, if a WRITE cycle begins in clock
18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM
MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03
Asynchronous inputs include the output enable
All READ, WRITE, and DESELECT cycles are initi-
To allow for continuous, 100 percent use of the data
2
cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The write data associated with the address
is required one cycle later, or on the rising edge of
clock cycle two.
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa# con-
trols DQa pins/balls; BWb# controls DQb pins/balls;
BWc# controls DQc pins/balls; and BWd# controls
DQd pins/balls. Cycle types can only be defined when
an address is loaded, i.e., when ADV/LD# is LOW. Par-
ity/ECC bits are only available on the x 18 and x36 ver-
sions.
high bandwidth and zero bus turnaround delays.
sramds) for the latest data sheet.
Dual Voltage I/O
function. The 2.5V V
I/O function.
18Mb: 1 MEG x 18, 512K x 32/36
Address and write control are registered on-chip to
The device is ideally suited for systems requiring
Please refer to Micron’s Web site
The 3.3V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
FLOW-THROUGH ZBT SRAM
DD
device is tested for 3.3V and 2.5V I/O
DD
device is tested for only 2.5V
(www.micron.com/
©2003 Micron Technology, Inc.