XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 528

• Manufacturer Part Number: XC908AS60ACFU
• Description: MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
• Manufacturer: Motorola Semiconductor Products

Byte Data Link Controller (BDLC)
27.8.2 Stop Mode
Technical Data
528
NOTE:
NOTE:
wake up and generate a CPU interrupt request if the interrupt enable (IE)
bit in the BDLC control register 1 (BCR1) is previously set. (See
Control Register 1
of a power saving, but the BDLC is guaranteed to receive correctly the
message which woke it up, since the BDLC internal operating clocks are
kept running.
Ensuring that all transmissions are complete or aborted before putting
the BDLC into wait mode is important.
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BDLC control register 1
(BCR1) is previously set. This is the lowest power mode that the BDLC
can enter.
A subsequent passive-to-active transition on the J1850 bus will cause
the BDLC to wake up and generate a non-maskable CPU interrupt
request. When a STOP instruction is used to put the BDLC in stop mode,
the BDLC is not guaranteed to correctly receive the message which
woke it up, since it may take some time for the BDLC internal operating
clocks to restart and stabilize. If a WAIT instruction is used to put the
BDLC in stop mode, the BDLC is guaranteed to correctly receive the
byte which woke it up, if and only if an end-of-frame (EOF) has been
detected prior to issuing the WAIT instruction by the CPU. Otherwise,
the BDLC will not correctly receive the byte that woke it up.
If this mode is entered while the BDLC is receiving a message, the first
subsequent received edge will cause the BDLC to wake up immediately,
generate a CPU interrupt request, and wait for the BDLC internal
operating clocks to restart and stabilize before normal communications
can resume. Therefore, the BDLC is not guaranteed to receive that
message correctly.
It is important to ensure all transmissions are complete or aborted prior
to putting the BDLC into stop mode.
Byte Data Link Controller (BDLC)
for a better understanding of IE.) This results in less
MC68HC908AZ60A — Rev 2.0
MOTOROLA
BDLC