XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 310

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XC908AS60ACFU

Manufacturer Part Number
XC908AS60ACFU
Description
MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
Manufacturer
Motorola Semiconductor Products
Datasheet
Serial Peripheral Interface (SPI)
19.14.1 SPI Control Register
Technical Data
310
Address:
The SPI control register:
SPRIE — SPI Receiver Interrupt Enable Bit
SPMSTR — SPI Master Bit
Reset:
Read:
Write:
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
1 = Master mode
0 = Slave mode
Enables SPI module interrupt requests
Selects CPU interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
Enables the SPI module
SPRIE
$0010
Bit 7
R
0
Serial Peripheral Interface (SPI)
Figure 19-11. SPI Control Register (SPCR)
= Reserved
R
6
0
SPMSTR
5
1
CPOL
4
0
CPHA
3
1
MC68HC908AZ60A — Rev 2.0
SPWOM
2
0
SPE
1
0
MOTOROLA
SPTIE
Bit 0
0

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