XC908AS60ACFU Motorola Semiconductor Products, XC908AS60ACFU Datasheet - Page 183
XC908AS60ACFU
Manufacturer Part Number
XC908AS60ACFU
Description
MC68HC908AZ60A, MC68HC908AS60A Hcmos Microcontroller Unit Technical Data
Manufacturer
Motorola Semiconductor Products
Datasheet
1.XC908AS60ACFU.pdf
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10.6 CGM Registers
10.6.1 PLL Control Register
MC68HC908AZ60A — Rev 2.0
MOTOROLA
Address:
Three registers control and monitor operation of the CGM:
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
PLLIE — PLL Interrupt Enable Bit
Reset:
Read:
Write:
•
•
•
This read/write bit enables the PLL to generate a CPU interrupt
request when the LOCK bit toggles, setting the PLL flag, PLLF. When
the AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
1 = PLL CPU interrupt requests enabled
0 = PLL CPU interrupt requests disabled
PLL control register (PCTL)
PLL bandwidth control register (PBWC)
PLL programming register (PPG)
$001C
PLLIE
Bit 7
0
Clock Generator Module (CGM)
Figure 10-4. PLL Control Register (PCTL)
= Unimplemented
PLLF
6
0
PLLON
5
1
BCS
4
0
3
1
1
Clock Generator Module (CGM)
2
1
1
CGM Registers
1
1
1
Technical Data
Bit 0
1
1
183
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