MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 8

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MSC8101DS

Manufacturer Part Number
MSC8101DS
Description
MSC8101 Network Digital Signal Processor
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
1-2
BNKSEL[0–2]
Note:
Refer to the System Interface Unit (SIU) chapter in the MCS8101 Reference Manual for details on how to
configure these pins.
see Figure 1-2
For the signals
multiplexed on
EOnCE Event
Ports A–D,
EE[2–3]
EE[4–5]
TC[0–2]
EED
EE0
EE1
PC[31–22, 15–12, 7–4]
PD[31–29, 19–16, 7]
SPARE1, SPARE5
Configuration
MODCK[1–3]
THERM[1–2]
GNDSYN1
PB[31–18]
PORESET
RSTCONF
VCCSYN1
BTM[0–1]
GNDSYN
PA[31–6]
VCCSYN
CLKOUT
HRESET
SRESET
DBREQ
RESET
Figure 1-1. MSC8101 External Signals
Port A
Port B
Port C
Port D
CLKIN
DLLIN
VDDH
TRST
TEST
GND
VDD
TMS
TDO
TCK
HPE
TDI
MSC8101 Technical Data
14
25
37
26
14
18
1
1
1
1
8
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
3
1
1
1
2
2
P
O
W
E
R
C
P
M
I
/
O
P
O
R
T
S
J
T
A
G
M
M
U
C
B
S
E
6
0
x
32
32
16
5
4
1
1
3
1
1
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
1
2
1
1
8
1
1
1
1
1
1
Reserved
A[0–31]
TT[0–4]
TSIZ[0–3]
TBST
IRQ1
BR
BG
ABB
TS
AACK
ARTRY
DBG
DBB
D[0–31]
D[32–47]
D[48–51]
D52
D53
D54
D55
D56
D57
D58
D59
D60
D[61–63]
Reserved
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
TA
TEA
NMI
NMI_OUT
PSDVAL
IRQ7
CS[0–7]
BCTL1
BADDR[27–28]
ALE
BCTL0
PWE[0–7]
PSDA10
PSDWE
POE
PSDCAS
PGTA
PSDAMUX
GBL
BADDR[29–31]
IRQ2
IRQ3
HD[0–15]
HA[0–3]
HCS1/HCS1
Single DS
Single HR
HDSP
HDDS
H8BIT
HCS2/HCS2
Reserved
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
INT_OUT
PSDDQM[0–7]
PUPMWAIT
HRW
HDS/HDS
HREQ/HREQ
HACK/HACK
HDI16 Signals
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ
HRRQ/HRRQ
Reserved
IRQ1
Reserved
Reserved
DREQ3
DREQ4
DACK3
DACK4
PSDRAS
PPBS
IRQ[2–3, 5]
EXT_BR2
EXT_BG2
EXT_DBG2
EXT_BR3
EXT_BG3
EXT_DBG3
IRQ6
IRQ7
PBS[0–7]
PGPL0
PGPL1
PGPL2
PGPL3
PGPL4
PGPL5

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