MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 25

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

The individual sets of externals signals associated with a specific protocol and data transfer mode are
multiplexed across any or all of the ports, as shown in Figure 1-2. The following sections provide detailed
descriptions of the signals supported by Ports A–Port D.
1.6.1
PA31
General-
Purpose
I/O
Time-Slot Assigner (TSA) that supports multiplexing from any of the SCCs, FCCs, SMCs, and two
MCCs onto four time-division multiplexed (TDM) interfaces. The TSA uses two Serial Interfaces (SI1
and SI2). SI1 uses TDMA1 which supports both serial and nibble mode. SI2 does not support nibble
mode and includes TDMB2, TDMC2, and TDMD2 which operate only in serial mode.
Port A Signals
FCC1: TXENB
UTOPIA master
FCC1: TXENB
UTOPIA slave
FCC1: COL
MII
Peripheral Controller:
Name
Dedicated Signal
Protocol
MSC8101 Technical Data
Table 1-7. Port A Signals
Dedicated
Direction
I/O Data
Output
Input
Input
FCC1: UTOPIA Master Transmit Enable
In the ATM UTOPIA interface supported by FCC1, TXENB is
asserted by the MSC8101 (UTOPIA master PHY) when there
is valid transmit cell data (TXD[0–7]).
FCC1: UTOPIA Slave Transmit Enable
In the ATM UTOPIA interface supported by FCC1, TXENB is
asserted by an external UTOPIA master PHY when there is
valid transmit cell data (TXD[0–7]).
FCC1: Media Independent Interface Collision Detect
In the MII interface supported by FCC1, COL is asserted by an
external fast Ethernet PHY.
Description
Port A Signals
1-19