MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 50

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

1-44
Port D Signals
General-
Purpose
PD29
I/O
SCC1: RTS, TENA
FCC1: RXADDR3
UTOPIA master
FCC1: RXADDR3
UTOPIA slave
FCC1: RXCLAV2
UTOPIA multi-PHY master,
direct polling
Peripheral Controller:
Name
Dedicated I/O
Protocol
Table 1-10. Port D Signals (Continued)
MSC8101 Technical Data
Direction
Dedicate
Output
Output
d I/O
Data
Input
Input
SCC1: Request to Send, Transmit Enable
Typically used in conjunction with CD supported by SCC2. The
MSC8101 SCC1 transmitter requests the receiver to send data
by asserting RTS low. The request is accepted when CTS is
returned low. TENA is the signal used in Ethernet mode.
FCC1: UTOPIA Multi-PHY Master Receive Address Bit 3
In the ATM UTOPIA master interface supported by FCC1 using
multiplexed polling, this is receive address bit 3.
FCC1: UTOPIA Slave Receive Address Bit 3
In the ATM UTOPIA slave interface supported by FCC1 using
multiplexed polling, this is receive address bit 3.
FCC1: UTOPIA Multi-PHY Master Receive Cell Available 2
Direct Polling
In the ATM UTOPIA master interface supported by FCC1 using
direct polling, RXCLAV2 is asserted by an external PHY when
one complete ATM cell is available for transfer.
Description