MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 53

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

General-
Purpose
PD16
PD7
I/O
FCC1: TXPRTY
UTOPIA
SPI: SPIMISO
SMC1: SMSYN
FCC1: TXADDR3
UTOPIA master
FCC1: TXADDR3
UTOPIA slave
FCC1: TXCLAV2
UTOPIA multi-PHY master,
direct polling
Peripheral Controller:
Name
Dedicated I/O
Protocol
Table 1-10. Port D Signals (Continued)
Direction
MSC8101 Technical Data
Dedicate
Output
Output
Output
Input/
d I/O
Input
Input
Input
Data
FCC1: UTOPIA Transmit Parity
In the ATM UTOPIA interface supported by FCC1, this is the
odd parity bit for TXD[0–7].
SPI: Master Input Slave Output
The SPI interface comprises four signals: master out slave in
(SPIMOSI), master in slave out (SPIMISO), clock (SPICLK),
and select (SPISEL). The SPI can be configured as a slave or
master in single- or multiple-master environments. When the
SPI is a slave, SPICLK is the clock input that shifts received
data in from SPIMOSI and transmitted data out through
SPIMISO.
SMC1: Serial Management Synchronization
Supported by SMC1. SMSYN is an input. The SMC interface
consists of SMTXD, SMRXD, SMSYN and a clock. Not all
signals are used for all applications. SMCs are full-duplex ports
that supports three protocols or modes: UART, transparent or
general-circuit interface (GCI).
FCC1: UTOPIA Master Transmit Address Bit 3
In the ATM UTOPIA master interface supported by FCC1 using
multiplexed polling, this is transmit address bit 3.
FCC1: UTOPIA Slave Transmit Cell Available 2
In the ATM UTOPIA slave interface supported by FCC1 using
multiplexed polling, this is transmit address bit 3.
FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 2
Direct Polling
In the ATM UTOPIA master interface supported by FCC1 using
direct polling, TXCLAV2 is asserted by an external UTOPIA
slave PHY to indicate that it can accept one complete ATM cell.
Description
Port D Signals
1-47