MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 65

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

RSTCONF
DBREQ/
EE0
HPE/EE1
BTM[0–1]/
EE[4–5]
No.
1
2
3
4
5
Pin
Required external PORESET duration minimum
Delay from deassertion of external PORESET to deassertion
of internal PORESET
Delay from deassertion of internal PORESET to SPLL lock
Delay from SPLL lock to DLL lock
Delay from SPLL lock to HRESET deassertion
CLKIN = 10 MHz
CLKIN = 100 MHz
CLKIN = 10 MHz
CLKIN = 100 MHz
CLKIN/SPLL PDF = 10 MHz
CLKIN/SPLL PDF = 30 MHz
DLL enabled
— BCLK = 20 MHz
— BCLK = 100 MHz
DLL disabled
DLL enabled
— BCLK = 20 MHz
— BCLK = 100 MHz
DLL disabled
— BCLK = 20 MHz
— BCLK = 100 MHz
Reset Configuration
Input line sampled by the MSC8101 at the rising
edge of PORESET.
EONCE Event Bit 0
Input line sampled after SC140 core PLL locks.
Holding EE0 high when PORESET is deasserted
puts the SC140 core into Debug mode.
Host Port Enable
Input line sampled at the rising edge of PORESET.
If asserted, the Host port is enabled, the PowerPC
system data bus is 32-bit wide, and the Host must
program the reset configuration word.
Boot Mode
Input lines sampled at the rising edge of
PORESET, which determine the MSC8101 Boot
mode.
Characteristics
Description
Table 2-10. External Configuration Signals
MSC8101 Technical Data
Table 2-11. Reset Timing
0
1
0
1
0
1
00 MSC8101 boots from external memory.
01 MSC8101 boots from HDI16.
10 Reserved.
11 Reserved.
Reset Configuration Master.
Reset Configuration Slave.
SC140 core starts the normal processing
mode after reset.
SC140 core enters Debug mode immediately
after reset.
Host port disabled (hardware reset
configuration enabled).
Host port enabled.
3073
3585
1024
512
Expression
800
16
—
CKIT
BCKT
RCT
BCKT
BCKT
CKIT
C
C
C
C
C
C
Settings
Min
160
1.6
153.65
179.25
102.4
10.24
26.67
30.73
35.86
80.0
25.6
5.12
0.0
Reset Timing
Max
—
—
Unit
2-11
ns
ns
s
s
s
s
s
s
s
s
s
s
s