MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 113

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

Maximum allowed ambient temperature is:
4.4
Each VCC and VDD pin on the MSC8101 should be provided with a low-impedance path to the board’s power
supply. Similarly, each GND pin should be provided with a low-impedance path to ground. The power supply
pins drive distinct groups of logic on the chip. The VCC power supply should be bypassed to ground using at
least four 0.1 µF by-pass capacitors located as closely as possible to the four sides of the package. The
capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should be kept to
less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as
VCC and GND planes.
All output pins on the MSC8101 have fast rise and fall times. Printed circuit board (PCB) trace interconnection
length should be minimized in order to minimize undershoot and reflections caused by these fast output
switching times. This recommendation particularly applies to the address and data busses. Maximum PCB
trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well
as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient currents
in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins.
There are 2 pairs of PLL supply pins: VCCSYN-GNDSYN and VCCSYN1-GNDSYN1. Each pair supplies
one PLL. To ensure internal clock stability, filter the power to the VCCSYN and VCCSYN1 inputs with a
circuit similar to the one in Figure 4-1. To filter as much noise as possible, place the circuit as close as possible
to VCCSYN and VCCSYN1. The 0.1-µF capacitor should be closest to VCCSYN and VCCSYN1, followed
by the 10-µF capacitor, and finally the 10-
GNDSYN and GNDSYN1 should be provided with an extremely low impedance path to ground and should be
bypassed to VCCSYN and VCCSYN1, respectively, by a 0.1-µF capacitor located as close as possible to the
chip package. The user should also bypass GNDSYN and GNDSYN1 to VCCSYN and VCCSYN1 with a
0.01-µF capacitor as closely as possible to the chip package
Layout Practices
P
P
P
P
P
TA = TJ – (PD
CORE
SIU
CPM
INT
D
= P
(50) = ((P
= P
(100) = ((P
INT
(200) = ((P
CORE
+ P
(200) + P
I/O
SIU
CPM
= 346 + 67 = 413
CORE
JA
– P
)
– P
LSI
SIU
VDD
Figure 4-1. VCCSYN and VCCSYN1 Bypass
– P
) / 100)
LCP
(50) + P
LCO
) / 150) 100 + P
)/300)
10
MSC8101 Technical Data
CPM
50 + P
resistor to VDD. These traces should be kept short and direct.
10 µF
(100) =168 + 36 + 142 = 346
200 + P
LSI
= ((70 – 2) / 100)
LCP
LCO
= ((210 – 6) / 150)
=((250 – 3) / 300
0.1 µF
VCCSYN
50 + 2 = 36
100 + 6 = 142
200 + 3=168
4-3