MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 16

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

1-10
TS
AACK
ARTRY
DBG
DBB
IRQ3
D[0–31]
D[32–47]
HD[0–15]
D[48–51]
HA[0–3]
Signal
Table 1-5. PowerPC System Bus, HDI16, and Interrupt Signals (Continued)
Input/Output
Input/Output Address Acknowledge
Input/Output
Input/Output
Input/Output Data Bus Most Significant Word
Input/Output
Input/Output
Input/Output
Data Flow
Output
Output
Input
Input
Input
Input
Input
Bus Transfer Start
Signals the beginning of a new address bus tenure. The MSC8101 asserts this signal
when one of its internal bus masters (SC140 core or DMA) begins an address tenure.
When the MSC8101 senses this pin being asserted by an external bus master, it
responds to the address bus tenure as required (snoop if enabled, access internal
MSC8101 resources, memory controller support).
A bus slave asserts this signal to indicate that it identified the address tenure. Assertion
of this signal terminates the address tenure.
Address Retry
Assertion of this signal indicates that the bus transaction should be retried by the bus
master. The MSC8101 asserts this signal to enforce data coherency with its internal
cache and to prevent deadlock situations.
Data Bus Grant
An output when an internal arbiter is used. The MSC8101 asserts this pin as an output
to grant data bus ownership to an external PowerPC bus master.
An input when an external arbiter is used. The external arbiter should assert this pin as
an input to grant data bus ownership to the MSC8101.
Data Bus Busy
The MSC8101 asserts this pin as an output for the duration of the data bus tenure.
Following a TA, which terminates the data bus tenure, the MSC8101 negates DBB for a
fraction of a bus cycle and then stops driving this pin.
The MSC8101 does not assume data bus ownership as long as it senses DBB is
asserted by an external bus master.
Interrupt Request 3
One of the eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
In write transactions the bus master drives the valid data on this bus. In read
transactions the slave drives the valid data on this bus. In Host Port Disabled mode,
these 32 bits are part of the 64-bit PowerPC data bus. In Host Port Enabled mode,
these bits are used as the PowerPC bus in 32-bit mode.
Data Bus Bits 32–47
In write transactions the bus master drives the valid data on this bus. In read
transactions the slave drives the valid data on this bus.
Host Data
When the HDI16 interface is enabled, these signals are lines 0-15 of the bidirectional
tri-state data bus.
Data Bus Bits 48–51
In write transactions the bus master drives the valid data on these pins. In read
transactions the slave drives the valid data on these pins.
Host Address Line 0–3
When the HDI16 interface bus is enabled, these lines address internal host registers.
MSC8101 Technical Data
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Description