MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 63

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2.5.1.2 Clocking and Timing Characteristics
CLKIN
Reference clock (CLKIN/PDF)
Bus Clock (BCLK)
Output Clock (CLKOUT)
Serial Communications Controller Clock (SCLK)
Communications Processor Module Clock (CPMCLK)
Baud Rate Generator Clock (BRGCLK)
SC140 core clock
Phase Jitter between BCLK and DLLIN
CLKIN frequency
CLKIN slope
DLLIN slope
CLKOUT frequency jitter
Delay between CLKOUT and DLLIN
Note:
Frequency
Input high
Input low
Cycle time
Frequency
Cycle time
Frequency
Cycle time
Frequency
Cycle time
Frequency
Cycle time
Frequency
Cycle time
For BRG DF = 4
— Frequency
— Cycle time
For BRG DF = 16 (default)
— Frequency
— Cycle time
For BRG DF = 64
— Frequency
— Cycle time
For BRG DF = 256
— Frequency
— Cycle time
Frequency
Cycle time
1
1.
3
3
Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep the
frequency after the predivider higher than 10 MHz.
Characteristic
(50% duty cycle)
(50% duty cycle)
1
Characteristics
Table 2-7. System Clock Parameters
Table 2-8. Clock Operation
MSC8101 Technical Data
Minimum
10
—
—
—
—
—
(0.01
CORET
Symbol
CPMT
CKOT
BRGT
BRGT
BRGT
BRGT
BCKT
COREf
CKIT
CKIT
CKIT
RCT
CPMf
CKOf
SCCf
BRGf
BRGf
BRGf
BRGf
BCKf
CKIf
ST
RCf
CLKOUT) + CLKIN jitter
C
C
H
C
L
C
C
C
C
C
C
C
Maximum
C
Clock and Timing Signals
100
0.5
5
2
5
6.25 MHz
1.56 MHz
10 MHz
213.3 ns
390 KHz
853.3 ns
10 MHz
20 MHz
20 MHz
25 MHz
50 MHz
25 MHz
75 MHz
33.3 ns
13.3 ns
6.67 ns
13.3 ns
53.3 ns
3.33 ns
10 ns
10 ns
10 ns
5 ns
5 ns
Min
2
100.0 MHz
18.75 MHz
4.69 MHz
1.17 MHz
100 MHz
100 MHz
150 MHz
300 MHz
13.33 ns
30 MHz
75 MHz
75 MHz
2.56 s
100 ns
100 ns
160 ns
640 ns
50 ns
50 ns
50 ns
50 ns
40 ns
20 ns
40 ns
Max
Unit
MHz
ns
ns
ns
ns
ns
2-9