MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 69

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2.5.3
2.5.3.1 Core Data Transfers
Generally, all MSC8101 bus and system output signals are driven from the rising edge of the input clock
(CLKIN). Memory controller signals, however, trigger on four points within a CLKIN cycle. Each cycle is
divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of CLKIN (and T3 at the
falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 2-12 shows.
Figure 2-4 is a graphical representation of Table 2-12.
Note:
Note:
Number
10
11
12
14
15
1:2, 1:3, 1:4, 1:5, 1:6
PLL Clock Ratio
Input specifications are measured from the TTL signal level (0.8 or 2.0 V) relative to the CLKIN rising edge.
PowerPC System Bus Access Timing
Hold time for all signals after CLKIN rising edge
AACK/ARTRY/TA/TEA/DBG/BG/BR setup time before CLKIN rising edge
Data bus setup time before CLKIN rising edge
a. Normal mode
b. ECC and parity mode
DP setup time before CLKIN rising edge
Setup time before CLKIN rising edge for all other signals
The UPM machine and GPCM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the internal tick. SDRAM
machine outputs change only on the CLKIN rising edge.
1:2.5
1:3.5
CLKIN
CLKIN
CLKIN
Figure 2-4. Internal Tick Spacing for Memory Controller Signals
T1
T1
T1
Table 2-12. Tick Spacing for Memory Controller Signals
Table 2-13. AC Characteristics for SIU Inputs
T2
T2
T2
3/10 CLKIN
4/14 CLKIN
1/4 CLKIN
MSC8101 Technical Data
T2
T3
T3
T3
Tick Spacing (T1 Occurs at the Rising Edge of CLKIN)
Characteristic
T4
T4
T4
1/2 CLKIN
1/2 CLKIN
1/2 CLKIN
T3
PowerPC System Bus Access Timing
for 1:2, 1:3, 1:4, 1:5, 1:6
for 1:2.5
for 1:3.5
11/14 CLKIN
8/10 CLKIN
3/4 CLKIN
Value
4.55
T4
0.5
6
4
5
6
Units
ns
ns
ns
ns
ns
ns
2-15