MSC8101DS Motorola / Freescale Semiconductor, MSC8101DS Datasheet - Page 59

• Manufacturer Part Number: MSC8101DS
• Description: MSC8101 Network Digital Signal Processor
• Manufacturer: Motorola / Freescale Semiconductor

2.5
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and
inputs. AC timings are based on a 50 pF load, except where noted otherwise, and 50
2.5.1
The following sections include a description of clock configuration and signal characteristics.
2.5.1.1 Clock Signal Configuration
Table 2-5 shows the maximum frequency values for internal (Core, Bus, SCC, CPM, and BRG) and external
(CLKOUT) clocks. The user must ensure that maximum frequency values are not exceeded.
Six bit values map the MSC8101 clocks to one of 64 configuration mode options. Each option determines the
CLKIN, SC140 core, PowerPC bus, SCC clock, CPM, and CLKOUT frequencies. The six bit values are
derived from three dedicated input pins (MODCK[1–3]) and three bits from the reset configuration word
(MODCK_H). To configure the SPLL pre-division factor, SPLL multiplication factor, and the frequencies for
the SC140 core, SCC clocks, CPM parallel I/O ports, and PowerPC buses, the MODCK[1–3] pins are sampled
and combined with the MODCK_H values when the internal power-on Reset (internal PORESET) is
deasserted. Clock configuration changes only when the internal PORESET signal is deasserted.
The following factors are configured:
The SCC division factor (SCC DF) is fixed at 4 and the CPM division factor (CPM DF) is fixed at 2. The BRG
division factor (BRG DF) is configured through the System Clock Control Register (SCCR) and can be 4, 16
(default after reset), 64, or 256.
Table 2-6 lists the available values for each of these configurable factors, as well as the 64 possible
configuration mode options.
Core Frequency
CPM Frequency (CPMCLK)
Bus Frequency (BCLK)
Serial Communication Controller Clock Frequency (SCLK)
Baud Rate Generator Clock Frequency (BRGCLK)
External Clock Output Frequency (CLKOUT)
AC Timings
SPLL pre-division factor (SPLL PDF)
SPLL multiplication factor (SPLL MF)
Bus post-division factor (Bus DF)
CPLL pre-division factor (CPLL PDF)
CPLL multiplication factor (SPLL MF)
Clock and Timing Signals
Characteristic
Table 2-5. Maximum Frequencies
MSC8101 Technical Data
Maximum in MHz
Clock and Timing Signals
300
150
100
100
transmission line.
75
75
2-5